The Difference and Application of SPI, UART, I2C Communication

Communication between electronic devices is like human conversation—both sides need a shared “language.” These languages are communication protocols.

I’ve written independent guides on SPI, UART, and I²C before. This article compares and contrasts them and fixes a few common misconceptions from older write-ups.

Ⅰ. Serial VS Parallel

Digital data is represented by bits (0/1). Bits are transmitted as voltage level changes. Note: logic “low” and “high” levels depend on the logic family (e.g., 3.3 V CMOS, 1.8 V, 5 V TTL)—not all systems use 0 V/5 V.

Parallel communication sends multiple bits at once on multiple lines; serial sends bits sequentially on one line (per direction). Parallel can be faster over very short distances but scales poorly (more pins, skew, crosstalk). Serial links dominate modern designs for pin efficiency and signal integrity.

Ⅱ. SPI communication

SPI (Serial Peripheral Interface) is a synchronous, full-duplex serial bus. Unlike UART or I²C, SPI streams arbitrary numbers of bits continuously without start/stop framing or addressing overhead.

Roles & naming (2025 terminology): Many vendors now prefer controller/target over the legacy master/slave; similarly some use COPI/CIPO instead of MOSI/MISO. This article uses controller/target with MOSI/MISO noted for familiarity.

Signals (typical 4-wire): SCLK (clock, from controller), MOSI (controller→target), MISO (target→controller), and CS/SS (chip select, active-low per target).

Key characteristics

• No inherent addressing—each target needs its own CS (or a decoder/expander).

• Clock polarity/phase defined by mode (0–3); one bit is transferred per clock edge per direction.

• Practical fan-out limited by signal integrity and loading on SCLK/CS lines.

Speed

SPI clocks commonly run from a few MHz up to tens of MHz (e.g., 10–50 MHz typical on many MCUs; higher on fast SoCs). Throughput is often far higher than I²C, not merely “~2×”.

Typical transaction

1. Controller configures mode/frequency and asserts the target’s CS low.

2. Clock runs; bytes/bits shift out on MOSI while response shifts in on MISO.

3. Controller deasserts CS to end the transfer (frame boundary).

Pros

• Very high throughput; full-duplex.

• Simple framing; low protocol overhead.

• Flexible word sizes (not limited to 8-bit).

Cons

• More pins/wires than I²C/UART (min. 4, plus one CS per target unless using expanders).

• No built-in acknowledgment or error detection—must be handled at higher layers.

• Cable length/fan-out limited by clocked single-ended lines.

Ⅲ. UART communication

UART (Universal Asynchronous Receiver/Transmitter) is a hardware block (often inside MCUs) that converts between parallel bytes and asynchronous serial frames on a TX/RX pair. It is a link layer, not a multi-drop bus protocol.

Because UART is asynchronous, there’s no shared clock line. Frames include start bit(s), data bits, optional parity, and stop bit(s). Popular formats: 8-N-1, 7-E-1, etc.

Baud rate tolerance (corrected)

For reliable links, the combined baud rate error between the two ends should generally be kept within about 2–3%; many designs aim for ≤2%. Some links can tolerate up to ~5% with margin; 10% is typically too high and risks framing errors, especially at higher baud rates.

Electrical levels

• TTL/CMOS UART (0–V_DD, e.g., 3.3 V) for on-board connections.

• RS-232 uses ± voltages and inversion (via a transceiver).

• RS-485 adds differential signaling and multi-drop support (not plain UART levels).

Pros

• Only two data wires (TX/RX) for point-to-point.

• No clock line; simple and well-understood.

• Optional parity for basic error detection.

Cons

• Point-to-point only at TTL levels (no native multi-drop without RS-485 or similar).

• Lower throughput than high-speed SPI; framing overhead reduces efficiency.

• Timing tolerance matters; clock mismatch causes framing errors.

Ⅳ. I²C communication

I²C was introduced by Philips (now NXP Semiconductors) and is a synchronous, two-wire, open-drain bus supporting multiple controllers and targets on the same two lines.

Lines: SDA (Serial Data) and SCL (Serial Clock). Correction: “SDA” stands for Serial Data (not “Serial Data Architecture”). Both lines require pull-up resistors; devices pull the line low to signal bits.

Frames & acknowledgments

• START, 7-bit (or 10-bit) address + R/W bit, data bytes (8 bits each), and ACK/NACK after every byte, ending with STOP.

• Clock stretching and bus arbitration enable multi-master operation.

Addresses (corrected)

With 7-bit addressing there are 128 codes, but several are reserved (general call, CBUS, 10-bit prefix, etc.). Usable device addresses are typically 112. 10-bit addressing expands the space (not commonly used in hobby-class parts).

Speeds (modes)

• Standard-mode: 100 kHz

• Fast-mode: 400 kHz

• Fast-mode Plus: 1 MHz

• High-speed mode: 3.4 MHz

• Ultra-Fast mode: 5 MHz (write-only, limited use)

Actual achievable speed depends on bus capacitance and pull-ups.

Pull-ups (updated note)

Values like 4.7 kΩ are common examples, but the correct resistor depends on V_DD, total bus capacitance, and required rise time from the I²C spec. For longer buses / higher speeds, use lower values (e.g., 2.2–3.3 kΩ) or active pull-ups.

Pros

• Only two wires regardless of device count.

• Built-in addressing and byte-level ACK/NACK.

• Supports multi-master and multi-target on one bus.

Cons (corrected)

• Slower than high-speed SPI; byte-oriented (8-bit) payloads.

• Open-drain with pull-ups limits speed and cable length.

• Hardware/driver handling is more complex than simple UART point-to-point.

Topologies

Single controller, multiple targets: Typical; ensure unique addresses (some devices allow pin-set address variants). Remember reserved address ranges.

Multiple controllers: Arbitration prevents collisions; devices must release the bus if they detect another controller driving a dominant ‘0’ while they output a ‘1’.

Ⅴ. Quick comparison & selection tips

Rules of thumb:

• Need speed and continuous streaming? Choose SPI.

• Need simple point-to-point or a console? Choose UART (mind baud accuracy).

• Need many low/medium-speed peripherals on two pins? Choose I²C (mind pull-ups & addressing).

Change log & corrections (since 2021)

• Clarified that logic levels vary by technology; not always 0/5 V.

• Replaced/augmented master/slave with controller/target; noted MOSI/MISO vs COPI/CIPO naming.

• SPI speed note updated: often far faster than I²C (not merely “~2×”).

• UART tolerance corrected: recommended combined baud error ≈2–3% (10% is not appropriate).

• I²C corrections: SDA = Serial Data (not “Architecture”); 7-bit usable addresses ≈112 due to reservations; added full speed-mode list; clarified pull-up sizing depends on bus capacitance and rise-time requirements.

• Fixed I²C pros/cons (removed “Hardware is simpler than UART” and an unrelated UART line that mentioned “baud rates within 10%”).