What is an ASIC Chip?

Ⅰ What is an ASIC chip?

ASIC (Application Specific Integrated Circuit ) chip is a dedicated integrated circuit, a proprietary application chip designed and manufactured from the root level in response to user requirements for a specific electronic system, whose computing power and computational efficiency can be customized according to algorithm needs, and is the product of fixed algorithm optimized design. ASIC chip modules can be widely used in artificial intelligence devices, virtual currency mining devices, consumable printing devices, military defense devices, and other intelligent terminals.

At the hardware level, ASIC chips are composed of basic silicon materials, gallium phosphide, gallium arsenide, gallium nitride, and other materials. At the physical structure level, ASIC chip modules are pieced together from IP cores such as external storage units, power managers, audio screen processors, and network circuits. The same chip module can carry one or several ASIC chips with the same or different functions to meet one or more specific needs.

ASICs are characterized by their user-specific requirements and have the advantages of smaller size, lower power consumption, increased reliability, improved performance, enhanced confidentiality, and lower cost when compared to general-purpose ICs in mass production.

An integrated circuit is a miniature electronic device or component. Using a certain process, the transistors, resistors, capacitors, and inductors required in a circuit and wiring interconnected together, made in one or several small semiconductor wafers or dielectric substrates, and then packaged in a shell, becoming a microstructure with the required circuit function. All components in the structure have been composed of a whole, so that electronic component towards miniaturization, low power consumption, intelligence, and high reliability. Integrated circuits were invented in the 1970s by Jack Kilby (integrated circuits based on germanium (Ge)) and Robert Noyes (integrated circuits based on silicon (Si)).

The larger the scale of the integrated circuit, the more difficult it is to set up a system for special requirements to change to solve these problems. Therefore, the emergence of special-purpose integrated circuits(ASICs) featuring user participation in design, which can achieve optimal design of the entire system, superior performance, and confidentiality. The ASICs can integrate the functions of several, dozens, or even hundreds of general-purpose medium- and small-scale integrated circuits on a single chip. And the whole system can be integrated on a single chip to achieve the system needs. It makes the whole circuit optimized. The number of components reduced, the wiring shortened, the volume and weight reduced, and the system reliability improved.

Ⅱ ASIC chip design process

First, the ASIC needs to be divided into internal functional modules so that each functional module implements the corresponding function. Each functional module is connected together to form the entire ASIC circuit. Second, the logic design of the modules is carried out in hardware description language (HDL) to form register transfer level (RTL) code according to the functional and interface requirements. Third, for the functional and timing requirements of the ASIC specification, write test code or test stimulus using field-programmable logic gate array (FPGA) prototype or software simulation to verify the logic and ensure that the logic design fully meets the design requirements. Fourth, the RTL code is mapped to the corresponding process library by the logic synthesis tool. Then layout and wiring and other layout designs are performed to complete timing verification and convergence to form the layout data for die production.

Ⅲ ASIC chip features

In contrast to conventional chips such as CPUs, which generate results by reading and executing external program code instructions, ASIC chips read raw input data signals and generate output signals directly after internal logic circuit operations.

1 Advantages

Compared with CPU, GPU, FPGA, and other types of chips, ASIC chips have multiple advantages in the application of dedicated systems, as shown in the following aspects.

① Area advantage: ASIC chips are designed to avoid redundant logic units, processing units, registers, storage units, and other architectures. They are built in the form of pure digital logic circuits, which help reduce the chip area. To deal with small area chips, the same size wafer can be cut out more number of chips, helping companies to reduce wafer costs.

② Energy consumption advantage: ASIC chips consume less energy per unit of arithmetic compared to CPU, GPU, and FPGA, such as GPU consumes about 0.4 watts of electricity per unit of arithmetic, and ASIC consumes about 0.2 watts of electricity per unit of arithmetic, which can better meet the energy consumption restrictions of new smart home appliances.

③ Integration advantage: ASIC chip system, circuit, and process are highly integrated due to custom design, which helps customers to obtain high-performance integrated circuits.

④ Price advantage: influenced by the small size, high operation speed, and low power consumption, ASIC chips are much less expensive than CPU, GPU, and FPGA chips. The current average price of ASIC chips in the global market is about $3. In the long term, if the mass production scale is reached, the price of ASIC chips is expected to keep decreasing.

2 Disadvantages

① ASIC chips are highly customized, with long design and development cycles, and the finished products need to do physical design and reliability verification.

② ASIC chips have a high dependence on algorithms. Artificial intelligence algorithms are updated and iterated at high speed, resulting in a high update frequency of ASIC chips.

③ The high degree of customization of ASIC chips and the relatively long R&D cycle expands the risk of ASIC finished products being eliminated from the market.

Ⅳ Classification of ASIC chips

ASIC chips Classification

(1) According to the degree of customization

ASIC chips can be classified as full-custom ASIC chips, semi-custom ASIC chips, and programmable ASIC chips.

① Full-custom ASIC chips

Full-custom ASIC chips are one of the most customized chips, in which developers design logic units for different functions based on different circuit structures, and build analog circuits, memory units, and mechanical structures on the chipboard. The logic cells are connected to each other by mask boards, and the ASIC chip mask boards are also highly customized.

Full-custom ASIC chips are expensive to design, with an average design time of more than 9 weeks per chip module. This type of chip is typically used for advanced applications.

Compared with semi-custom ASIC chips, full-custom ASIC chips are superior in terms of performance and power consumption. For the same function, the average arithmetic output of a full-custom ASIC chip is about 8 times the average arithmetic output of a semi-custom ASIC chip under the same process, and the performance of a full-custom ASIC chip with a 24nm process is better than that of a semi-custom ASIC chip with 5nm process.

② Semi-custom ASIC chips

Most of the logic cells of semi-custom ASICs are taken from the standard logic cell library, and some of them are custom designed according to specific requirements. The design cost is lower and the flexibility is higher than that of the full custom ASIC chip.

Depending on the number of standard logic cells and custom logic cells, semi-custom ASICs can be subdivided into gate array chips and standard cell chips.

a. Gate Array ASIC Chip

Gate array ASIC chip includes channeled gate array, channelless gate array, and structured gate array. Gate array ASIC chip structure on the silicon wafer predetermined transistor position can not be changed, the designer mostly through the change of the chip bottom metal layer and other ways to adjust the logic unit interconnection structure.

Channeled gate array ASIC chips: the transistor positions of these chips are highly fixed, and designers can lay out the circuits in the predefined blank space between the transistor rows.

Channeled gate array ASIC chip

Channelless gate array ASIC chips: In the channelless structure, there is no circuit layout space between the transistor rows, and designers usually wire above the gate array cells.

Channelless gate array ASIC chip

Structured gate array ASIC chip: This structure consists of a basic gate array row and an embedding block. The embedding block increases the flexibility of the circuit layout but places a limit on the chip size. With this structure, the line layout area is used more efficiently, the design cost is lower, and the turnaround time is shorter.

Structured gate array ASIC chip

b. Standard Cell ASIC chip

This type of ASIC chip consists of logic cells selected from a library of standard cells. Designers can arrange the standard cells according to their algorithm requirements. In addition to standard cells, fixed blocks such as microcontrollers and microprocessors can also be used in the standard cell ASIC chip architecture.

Standard Cell ASIC Chip

③ Programmable ASIC chip

Programmable ASIC chips can be divided into FPGA chips and PLD chips. In actual production, the number of research institutions and companies that classify FPGA chips as different from ASIC chips is increasing, so this report only considers PLD (Programmable Logic Device) as a subcategory of programmable ASIC chips.

PLDs, also known as programmable logic devices, include a matrix of basic logic cells, flip-flops, latches, etc. in their structure, and their interconnected parts exist as individual modules. Designers can program PLDs to meet some of their custom application requirements.

(2) According to the terminal function

ASIC chips can be classified as TPU chips, BPU chips, and NPU chips depending on the terminal function.

① TPUs are tensor processors, dedicated to machine learning. For example, Google developed in May 2016 a programmable AI accelerator for the Tensorflow platform, a programmable AI gas pedal with an internal instruction set that runs when the Tensorflow program changes or updates its algorithms.

② BPU is Brain Processor, an embedded AI processor architecture proposed by Horizon Technology.

③ NPU is a neural network processor that emulates human neurons and synapses at the circuit layer and directly processes large-scale electronic neuron and synapse data with a deep learning instruction set.

Ⅴ ASIC chip products introduction

① Google launched TPU in 2016, and Google's 2017 version of AlphaGo physical processor is embedded with 4 TPUs, which can support the Google Cloud TPU platform and machine-learning supercomputer.

② IBM launched the second generation TrueNorth chip with a 28nm process in August 2014 by simulating brain structure, which can be applied to real-time video processing.

③ Intel introduced the Xeon family of ASIC chips in 2017. This series of chips can act as a standalone processor without the need for additional host processors and auxiliary processors and can be applied to machine deep learning.

④ Stanford University introduced ASIC chips based on a new neuromorphic computing architecture with a computing speed of 9,000 times that of an ordinary computer, which can simulate about 1 million brain neurons and billions of synaptic connections.

⑤ Emerging science and technology companies are expanding the application of ASIC chips to security, assisted driving, traditional home appliances, smart medical, and other fields.