Random Access Memory: Definition, Types and Working

Catalog

Ⅰ Definition of random access memory

Memory is a component used to store large amounts of information in a digital system and is an important part of computers and digital devices. Memory can be divided into two categories: random access memory (RAM) and read-only memory (ROM).

Random access memory (RAM)

Random access memory (RAM) can store information into and read information from a specified cell. Any information stored in RAM will be lost after power off, so RAM is a volatile memory. ROM is a read-only memory, in addition to fixed storage of data, tables, and firmware, it also has a wide range of uses in combinational logic circuits.

Ⅱ Features of random access memory

1. Random access

The so-called "random access" means that when the data in the memory is read or written, the time required has nothing to do with the location of the piece of information or the location where it is written. In contrast, when reading or writing information in a sequential access storage device, the required time and location will be related. A random access memory is mainly used to store operating systems, various applications, data, etc.

When RAM is in a normal working state, you can read data from RAM or write data to RAM. Compared with ROM, RAM has the advantages of convenient reading/writing and flexible use and is especially suitable for occasions where data is frequently changed quickly.

2. Volatile

When the power is off, RAM cannot retain data. If you need to save data, you must write them to a long-term storage device (such as a hard disk). The working characteristic of RAM is that after power-on, data information can be accessed at any location unit at any time, and internal information will disappear after power off.

3. Sensitive to static electricity

Just like other sophisticated integrated circuits, random access memory is very sensitive to environmental electrostatic charges. Static electricity will interfere with the charge of the capacitor in the memory, causing data loss and even burning out the circuit. Therefore, you should touch the metal ground with your hand before touching the RAM.

4. Access speed

Modern random access memory has the fastest writing and reading speed among almost all access devices, and the access delay is also insignificant compared with other storage devices involving mechanical operations.

5. Need to refresh (regeneration)

Modern random access memories rely on capacitors to store data. A fully charged capacitor represents 1 (binary), and an uncharged capacitor represents 0. Since the capacitors are more or less leaky, if no special treatment is made, data will gradually be lost over time. Refresh is to read the state of the capacitor in a specified period and then recharge the capacitor according to the original state to make up for the lost charge. The need to refresh just explains the volatility of random access memory.

Ⅲ Composition of random access memory

RAM is composed of a storage matrix, address decoder, read/write controller, input/output, chip selection control, etc.

Composition of random access memory

(1) Storage matrix. As shown in the figure, the core part of RAM is a register matrix, which is used to store information, called a storage matrix.

(2) Address decoder. The function of the address decoder is to translate the binary number corresponding to the registered address into an effective row selection signal and column selection signal, thereby selecting the storage unit.

(3) Read/write controller. When accessing RAM, whether to read or write to the selected register is controlled by reading and write signals. During the read operation, the data of the selected unit is transmitted to the CPU (central processing unit) via the data line and the input/output line; during the write operation, the CPU saves the data to the selected unit via the input/output line and the data line.

(4) Input/output. RAM exchanges data with the computer's CPU through the input/output terminal. It is the output terminal when reading, and it is the input terminal when writing. It is dual-purpose in one line and is controlled by the read/write control line. The number of data lines at the input/output end is the same as the number of register bits corresponding to an address, and the input/output ends of some RAM chips are separated. Generally, the output terminal of RAM has an open collector or tri-state output structure.

(5) Chip selection control. Due to the limitation of RAM integration, the memory system of a computer is often composed of many RAMs. When the CPU accesses the memory, it can only access a certain piece (or several pieces) of RAM at a time. That is, only one piece (or several pieces) of RAM in the memory is accessed by the CPU and exchanges information with it, while other pieces of RAM do not contact the CPU. The chip selection is used to achieve this control. Usually, a piece of RAM has one or several chip selection lines. When a chip selection line of a certain chip is connected to a valid level, the chip is selected, and the output signal of the address decoder controls the register of a certain address of the chip to connect with the CPU. When the chip select line is connected to the invalid level, the chip and the CPU are in a disconnected state.

Ⅳ Types of random access memory

According to the different working principles of the storage unit, RAM is divided into static RAM (SRAM) and dynamic RAM (DRAM).

1. Static random access memory (SRAM)

The static storage unit is formed by adding a gate control on the basis of a static trigger. Therefore, it stores data by the self-protection function of the trigger. The information stored in the SRAM can be retained for a long time without power failure. The state is stable, and no external refresh circuit is required, which simplifies the external circuit design. However, due to the large number of transistors contained in the basic storage circuit of SRAM, the integration level is low and the power consumption is high.

Typical structure of static random access memory

T5, T6, T7, and T8 are all gated control tubes. As long as the gate is high, these tubes work in the variable resistance area and act as switches.

Among them, the storage unit is connected to the data line (bit line) through T5, T6; the data line is connected through T7, T8, and then through the input/output buffer circuit and the input/output line to realize the transmission and exchange of information. In the operation process of writing information, before writing information for the first time, the information in the storage unit is random information.

Suppose you want to write information "1":

1) The address code is added. After the address is valid, the corresponding row selection line X and column selection line Y are both high, and T5, T6, T7, and T8 are conductive;

2) Chip select signal is valid (low level);

3) The write signal is valid. At this time, the three-state gates G2 and G3 are in a working state, G1 outputs a high-impedance state, and the information "1" reaches the Q terminal through G2, T7, and T5; after the inversion of G3, the information "0" passes through T8, T6 reached. T4 is conductive and T3 is off. Obviously, the information "1" has been written into the memory cell.

Suppose you want to read the information "1":

1) The address code for accessing the address unit is valid;

2) Chip select valid =0;

3) The read operation is valid R/=1; at this time: the three-state gate G1 is in working state, G2 and G3 are high-impedance states, and the information "1" in the memory cell is read through the T5, T7, and G1 three-state gates.

In addition to the above-mentioned static SRAM of the NMOS structure, there are the following types of SRAM.

SRAM with CMOS structure: lower power consumption and larger storage capacity.

Bipolar structure SRAM: higher power consumption, faster access speed.

Features of SRAM

●Storage principle: the data is stored by the trigger.

●Unit structure: Six-tube NMOS or OS structure.  

●Advantages: fast speed, easy to use, no need to refresh, very low static power consumption; often used as Cache.  

●Disadvantages: a large number of components, low integration, and high operating power consumption.

●Commonly used SRAM integrated chips: 6116 (2Kx8 bits), 6264 (8Kx8 bits), 62256 (32Kx8 bits), 2114 (1Kx4 bits).

2. Dynamic Random Access Memory (DRAM)

DRAM uses the principle of storing electric charges in capacitors to store information, with simple circuits and high integration. Since any capacitor has leakage current, when the capacitor stores electric charge, the electric charge will be lost due to the discharge of the capacitor over a period of time, and the stored information will be lost. The solution is to read and rewrite the DRAM every certain time (usually 2ms) so that the charge discharged on the capacitor that was originally at the logic level "l" is replenished. The capacitance at the level "0" still remains "0". This process is called DRAM refresh.

The refresh operation of DRAM is different from the memory read/write operation, mainly in the following points:

(1) The refresh address is generated by the refresh address counter, not provided by the address bus.

(2) The basic memory circuit of DRAM can be refreshed at the same time by row, so refresh only needs row address, not column address.

(3) The data line of the memory chip is in a high-impedance state during a refresh operation, that is, the on-chip data line is completely isolated from the external data line.

Compared with SRAM, DRAM has the advantages of high integration, low power consumption, and low price, so it is widely used in large-capacity memory. The disadvantage of DRAM is that the logic circuit needs to be refreshed, and normal read and write operations cannot be performed during refresh operations.  

Typical structure of dynamic random access memory

The gate control tubes T3, T4, T5, T6, T7. T8, C1, C2 are MOS capacitors.

DRAM read/write operation process:

1) The address to access the storage unit is valid; 2) The chip selection signal is available (not shown); 3) A control signal for reading out information or writing new information is issued.

During the read operation, make the original information Q=1, C2 is charged after the address is valid, the row and column selection lines are high; after adding the chip select signal, send the read signal R=1, W=0; T4, T6, and T8 are conductive and read through T4, T6, and T8. During the write operation, assume that the original information is "0" and the information "1" is to be written. After the address of the storage unit is valid, X and Y are high; after the chip select signal arrives, add the write command W= 1, R=0, that is, "1”. Information is charged to C2 through T7, T5, and T3. After charging to a certain voltage, T2 conducts electricity, C1 discharges, and T1 cuts off, so Q becomes high level, and "1" information is written Into the memory cell. If the written information is "0", the charge on the original capacitor remains unchanged.

Dynamic RAM refresh: Because DRAM relies on MOS capacitors to store information. When the information is not processed for a long time, the charge on the capacitor will gradually be lost due to leakage and other reasons, resulting in the loss of stored data. Replenishing charge in time is a very important issue in dynamic RAM. The process of recharging is called "refresh"—Refresh is also called "regeneration".

Supplementary charging process: add pre-charge pulse  , pre-charge tube T9, T10 conduction, C01, C02 quickly charge to VDD. After cancellation of , the charge on C01, C02 is maintained. However, the read operation is performed: the address is valid, and the row and column selection lines X and Y are high; R=1, W=0 for the read operation, if the original information is Q="1", it means that the MOS capacitor C2 has charge. C1 has no charge (that is, T2 is conductive, and T1 is off). At this time, the charge on C01 will supplement C2, and the charge on C02 will be discharged through the T2 conductive tube, resulting in supplementary charging of C2. The read data is still , then DO=1.

In fact, before each read operation, the DRAM must be refreshed once in a row, that is, a precharge pulse is added first, and then the read operation is performed. At the same time, when not performing any operation, the CPU should also charge the dynamic RAM at regular intervals (usually 2mS time) to make up for the charge loss.

Features of DRAM  

●Storage principle: the principle of using MOS tube gate capacitance to store charge, which needs to be refreshed (early: three-tube basic unit; later: single-tube basic unit).

●Refresh (regeneration): In order to replenish the leaked charge in time to avoid the loss of stored information, it is necessary to periodically replenish the charge to the gate capacitor.  

●Refresh time: the time for a regular refresh operation. The time must be less than the time that the gate capacitance naturally retains information (less than 2ms).

●Advantages: The integration is much higher than SRAM and its power consumption and price are low.

●Disadvantages: The peripheral circuit is complicated due to the need to refresh; refresh also makes the access speed slower than SRAM. So in computers, DRAM is often used as the main memory.

Nevertheless, due to the simple structure of the DRAM memory cell, fewer components, high integration, and low power consumption, it has become the mainstream product of large-capacity RAM.

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