Apple M1 Ultra -- The Technology Behind the Chip Interconnection

Published: 12 March 2022 | Last Updated: 12 March 20224154
Nowadays, manufacturing high-performance microprocessors are becoming increasingly tricky and expensive. That's why developers must choose complex packaging technologies and designs for performance-demanding applications. Apple acknowledges that it had to fuse two M1 Max system chips together to build the M1 Ultra processor. But it did not say it had to use one of TSMC's most advanced packaging technologies to build the M1 Ultra.
This video introduces the details of Apple M1 Ultra.

M1 Ultra — How Apple DESTROYED Nvidia


Apple M1 Ultra (1).png 


Nowadays, manufacturing high-performance microprocessors are becoming increasingly tricky and expensive. That's why developers must choose complex packaging technologies and designs for performance-demanding applications. Apple acknowledges that it had to fuse two M1 Max system chips together to build the M1 Ultra processor. But it did not say it had to use one of TSMC's most advanced packaging technologies to build the M1 Ultra.

Fortunately, unofficial sources are not as secretive as Apple and were able to dig up more details about the interconnect between Apple's UltraFusion processors. The processor offers 2.5 TB/s of bandwidth. Media reports indicate that Apple's M1 Ultra processors are built using TSMC's CoWoS-S (wafer-on-chip substrate with silicon interposer) 2.5D interposer-based packaging process for the M1 Ultra. AMD, Nvidia, and Fujitsu are among the companies using similar technology to build high-performance processors for data centers and high-performance computing (HPC).


There is no doubt that Apple's M1 Ultra is a powerful design. Each M1 Max SoC has a die size of 432mm². So the M1Ultra must use more than 860mm² of intermediate layers. AMD and Nvidia use larger intermediate layers and their compute GPUs have high bandwidth memory. 


Apple M1 Ultra (2).png


But TSMC's CoWoS-S is not the world's largest semiconductor manufacturer's only option for bandwidth-intensive applications. Some experts speculate that Apple may choose TSMC's InFO_LSI technology for ultra-high-bandwidth small-chip integration. Unlike CoWoS-S, InFO_LSI uses local silicon interconnects rather than large and expensive intermediary layers. Intel's Embedded Chip Interconnect Bridge (EMIB) uses the same concept.

 

Apple showed an M1 Max die shot with a large I/O pad, similar to a native interconnect designed to connect to an intermediate chip. Therefore, it is not surprising that many believe Apple uses InFO_LSI. 

 

TSMC 3DFabric.png

 

But there may be a reason why Apple is sticking with the more expensive CoWoS-S. TSMC's InFO_LSI officially launches in August 2020 and is scheduled to be certified by Q1 2021. Meanwhile, Apple's M1 Max will enter mass production in Q2 or Q3 of 2021. So Apple may simply not have enough time to implement InFO_LSI, or it may decide not to take any chances and stick with well-known technologies that are widely used by various companies.  


Apple M1 Ultra.png 

 

DigiTimes revealed that Unimicron Technology is currently Apple's only ABF substrate supplier, as it is the only company that can provide the quality and quantity Apple needs. In any case, while we now know what packaging technology Apple is using to implement UltraFusion interconnect, we still don't know its clocking, bus width, power, etc.

 

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