Dynamic On-Resistance and its Impact on Power Converters

Gallium nitride (GaN) devices are significantly enhancing various dimensions of power electronics, thereby leading to a revolutionary transformation in this field. Nevertheless, there are notable differences in its parameters, which result in many unique stability issues.

In gallium nitride high-electron mobility transistors (GaN HEMTs), parametric instability is typically linked to their trapping behavior. The three main challenges with parametric stability that GaN HEMTs face while switching normally are dynamic ON resistance, output capacitance loss, and dynamic threshold voltage.

Ⅰ. How can Dynamic ON-resistance cause parametric stability issues in power converters?

A well-known problem in GaN HEMTs is dynamic (), where  is larger than its measured dc value following severe blocking voltage stress. does not frequently appear in datasheets, although it causes unfavorable increases in the device's conduction loss and junction temperature.

Especially for high-frequency applications, this , presents significant design issues for GaN-based power converters. Various factors affecting the  are its physical characteristics, factors affecting the number of trapped electrons, and the characterization approach.

Ⅱ. Physical Characteristics

The trapping effect can cause to develop in a number of different parts of the GaN HEMT's structure. Charge trapping could happen in the buffer layer, the GaN channel, the gate region, close to the surface, and/or in the dielectric due to the following reasons:

● Leakage current electrons being inserted under high drain bias

● Hot electrons are created during switching transitions, which are the result of the overlapping of high voltage and high current

All of them have the potential to lessen 2DEG conductivity while simultaneously raising . At the device level, a number of methods have been put forth to lessen trapping effects and solve the problem, including

● Surface passivation optimization

● Intricately constructed GaN buffers

● Ideal field-plate structures

The typical variation of GaN HEMTs during a switching event is seen in Fig. 1. increases primarily in two stages:

● Hard turn-ON

● OFF-state

Fig. 1. variation during a switching event of GaN HEMTs. Source: IEEE Transactions on Power Electronics

Hard Turn-ON

The hard turn-ON process has a more significant impact on the than the OFF-state process. The hard turn-ON stress causes electron trapping both in the buffer and at the interface that lies between AlGaN and the passivation layer.

According to several studies, interface/surface trapping predominate during the hard turn-on process while observing the effect buffer region and the drain field plate. The energy level of the traps crucial to the hard turn-on process is widely dispersed but relatively shallow.

OFF-State

The OFF-state stress primarily causes electron trapping in the buffer. Detrapping these electrons in the on-state enables them  to gradually return to their static values. In most GaN HEMTs, it should be noted that the soft turn-ON procedure is not anticipated to cause considerable .

Ⅲ. Factors Affecting the Quantity of Trapped Electrons

Numerous research studies have documented the impact of various operating circumstances of power converters on the , since the is caused by the device switching transition. There are many factors that have a significant impact on the number of trapped electrons, such as

● Blocking voltage

● Drain-to-source voltage

● Nonmonotonic relationship between  and OFF-states.

● Load current 

● Switching speed

● Switching frequency and duty cycle

● Junction temperature 

● Hard switching

● Soft switching

The load current (), notably during the hard turn-on phase, influences the hot-electron acceleration and subsequently the trapping efficacy. As rises, a higher therefore appears. The amount of hot electrons trapped depends on switching speed (and duration).

Therefore, a higher gate resistance could lead to the more significant problem. A smaller is caused by a faster detrapping process that is made possible by a higher gate current or gate voltage.

must rely on switching frequency and duty cycle since the time constant of trapping behavior can range from nanoseconds to seconds. Junction temperature and the likelihood of electron entrapment and detrapping are both correlated. There are conflicting reports for a number of devices that the either rises or falls at greater or exhibits more intricate dependencies.

Finally, although the  has differences between hard switching and soft switching, its dependence may vary depending on the device.

Ⅳ. Characterization Test

Despite significant efforts in characterizations, significant inconsistencies have been recorded, even for commercial devices, ranging from a little increase to a ten times larger gain over static . It was recently brought up that the characterization methods are significantly responsible for this difference.

The three most popular ways to describe  are

● Pulse I-V test

● Double-pulse test (DPT)

● Steady-state continuous-switching test

Pulse I-V Test

The pulse I–V test is usually done at the wafer level with a resistive load. This test is used in many trapping physics studies. The overlap of current and voltage could be changed to replicate hard or soft switching, but it couldn't replicate the switching locus and slew rate (dv/dt) in real-time applications.

Double-Pulse Test

The traditional DPT technique, as advised by the JEDEC standard, has been applied to a number of inductive load circuit topologies. However, because DPT neglects the accumulation effects of repeated switching cycles, it may incorrectly calculate the device  in continuous-switching power converters. Additionally, the OFF-state stress time prior to the first pulse is typically not specified by DPT, which could cause uncertainty in .

Steady-State Continuous-Switching Test

Modern  test design has recently concentrated on the continuous-switching technique, which switches GaN devices to the steady state in power converters like half-bridge topologies, buck converters, resonant converters, etc. The optimum method for doing a characterization with a realistic application profile is a steady-state continuous-switching test.

It is notable that has been carried out at the wafer level for continuous-switching converters, which could greatly speed up the development of GaN HEMTs.

For this on-wafer dynamic characterization to work, the parasitics of the whole system, like the probe tip, connectors, and cables, must be carefully controlled. This allows for high switching speeds, switching voltages, and switching currents.

To conclude,  characterized in application-use settings offers useful references for converter design and performance assessment.  has a direct impact on the efficiency of GaN-based converters because of the elevated conduction loss.

Ⅴ. Summarizing the Key Points

● Dynamic on-resistance occurs when the on-resistance of a GaN device is larger than its measured DC value following severe blocking voltage stress.

● Physical features, factors impacting the quantity of trapped electrons, and the method of characterization are all important components of the dynamic on-resistance.

● Blocking voltage, drain-to-source voltage, OFF-states, load current, switching speed, switching frequency and duty cycle, junction temperature, hard switching and soft switching, etc. are the factors affecting the quantity of trapped electrons.

● Dynamic on-resistance is a critical parameter that must be carefully controlled to ensure the stability, reliability, and robustness of GaN power devices.

Ⅵ. Reference

Kozak, Joseph Peter, Ruizhe Zhang, Matthew Porter, Qihao Song, Jingcun Liu, Bixuan Wang, Rudy Wang, Wataru Saito, and Yuhao Zhang “Stability, Reliability, and Robustness of GaN Power Devices: A Review.” IEEE Transactions on Power Electronics 38, no. 7 (July 2023): 8442–71. https://doi.org/10.1109/tpel.2023.3266365.