Current Shunt Resistor Pulse Rating Selection: Sizing for Inrush Energy, TCR Drift, and Kelvin Connections

This technical guide establishes a selection and verification framework for sizing low-ohmic current shunt resistors in power conversion and motor drive systems, targeting power supply, motor control, and analog front-end engineers.

Selecting a current shunt resistor requires evaluating two distinct thermal and electrical regimes: steady-state power dissipation and transient pulse energy. While continuous current sizing relies on Terminal Part Temperature ($T_K$) derating and Temperature Coefficient of Resistance (TCR) drift, transient inrush events—such as motor startup and capacitive charging—are strictly adiabatic, where energy is stored within the alloy mass before conduction begins. Sizing a precision shunt demands validating pulse energy ($E=\int i^2(t)Rdt$) against surge curves, eliminating solder joint resistance via 4-terminal Kelvin architectures, and suppressing equivalent series inductance ($L_{\text{ESL}}$) spikes during high$di/dt$switching.

Transient Pulse Energy: Physics of Adiabatic Heating vs. Continuous Dissipation

Transient pulse survivability in current shunts depends on the resistive alloy's thermal mass absorbing energy adiabatically during short intervals ($t<1\text{to}10\text{ms}$), rendering continuous average power ratings irrelevant for inrush and short-circuit events.

The Adiabatic Thermal Boundary ($t<1\text{ms}$to$10\text{ms}$)

Under continuous operating conditions, heat generated in a current shunt resistor conducts through the terminal solder joints into the printed circuit board (PCB) copper planes, establishing thermal equilibrium. However, when an electrical system experiences a rapid current spike—such as a motor locked-rotor event, inverter leg shoot-through, or capacitive pre-charge—the energy injection occurs faster than thermal conduction can transport heat away from the resistive element.

For pulse durations typically shorter than$1\text{ms}$to$10\text{ms}$, heat transfer to the environment and PCB is essentially zero. The energy dissipation during this interval is governed by adiabatic heating^[1], where 100% of the generated thermal energy is stored directly within the specific heat capacity of the resistive alloy mass:

$$E_{\text{pulse}}={\int }_0^{t_p}{i}^2(t)·Rdt=m·c_p·\Delta T$$

Where:

• $E_{\text{pulse}}$is the transient pulse energy in Joules ($\text{J}$).

• $i(t)$ is the instantaneous current as a function of time.

• $R$is the nominal resistance of the shunt element ($\Omega$).

• $m$is the active mass of the resistive alloy ($\text{kg}$).

• $c_p$is the specific heat capacity of the alloy ($\text{J}/(\text{kg}{·}^{\circ }\text{C})$).

• $\Delta T$is the instantaneous temperature rise within the alloy (${}^{\circ }\text{C}$).

If the energy delivered during this transient exceeds the alloy's thermal absorption limit, the internal element temperature spikes exponentially. This local thermal stress causes lattice dislocation, micro-cracking at electron-beam weld seams, or outright melting of the resistive core. Consequently, a resistor whose calculated average continuous dissipation ($P_{\text{avg}}=I_{\text{rms}}^{2}R$) consumes only 20% of its rated wattage can burn open during its very first startup cycle if the adiabatic surge limit is exceeded.

Standard qualification testing establishes the baseline non-destructive boundary for short-duration loads. Under IEC 60115-1 Clause 4.13 and JIS C 5201-1 Clause 4.13^[7], the Short-Time Overload (STOL) test subjects the resistor to$5\times$rated continuous power (or$2.5\times$to$5\times$the Rated Continuous Working Voltage, RCWV) for a duration of 5 seconds. To pass the qualification, the component's permanent resistance drift must satisfy:

$$\Delta R\le \pm (0.5\%+0.05\Omega )$$

While STOL tests verify mid-duration endurance (seconds), microsecond- and millisecond-scale pulses must be calculated directly against manufacturer-published pulse energy curves.

Calculating Inrush Pulse Energy for Real-World Waveforms

To size a current shunt resistor against surge ratings, arbitrary current transients must be converted into their Joule equivalents ($E=\int i^2(t)Rdt$). In motor drives and switch-mode power supplies, transients typically match one of three geometric current waveforms:

1. Rectangular Inrush Pulses (e.g., clamped fault currents, pulsed braking):

   $$E=I_{\text{pk}}^2·R·t_p$$

2. Triangular or Linear Decay Pulses (e.g., inductor discharge, motor commutation surges):

   $$E=\frac{1}{3}·I_{\text{pk}}^2·R·t_p$$

3. Capacitive Exponential Decay (e.g., DC-link pre-charging, capacitive bus coupling):

   $$E=\frac{1}{2}·I_{\text{pk}}^2·R·\tau$$

   (where$\tau =R_{\text{loop}}C$, and$t_p\approx 5\tau$covers $99.3\%$ of total dissipated energy).

Once total pulse energy ($E$) is determined, designers calculate an equivalent single-pulse peak power ($P_{\text{eq}}$) over pulse duration$t_p$:

$$P_{\text{eq}}=\frac{E}{t_p}$$

This value ($P_{\text{eq}}$at$t_p$) is the exact coordinate plotted against the component's datasheet pulse curves.

Interpreting Manufacturer Pulse Rating Curves: Single Pulse vs. Continuous Pulse Trains

Datasheet pulse curves plot permissible peak power ($P_{\text{pk}}$) or maximum energy ($E_{\text{max}}$) on a logarithmic scale across time durations spanning$10\mu \text{s}$to$10\text{s}$. Correct interpretation requires distinguishing between isolated single-pulse events and repetitive pulse trains:

• Single-Pulse Limit: Applies strictly when the resistor begins at a baseline temperature ($T_K\le {70}^{\circ }\text{C}$or${25}^{\circ }\text{C}$, depending on manufacturer documentation) and has ample time to cool completely between events (typically$>10\text{to}60\text{seconds}$).

• Repetitive Pulse Trains: When pulses occur repetitively (e.g., PWM cycles or cyclic motor acceleration), average power dissipation must be calculated:

  $$P_{\text{avg}}=E_{\text{pulse}}·f_{\text{sw}}$$

  Here, the designer must satisfy two independent checks:$P_{\text{avg}}$must remain below the continuous derated power limit at the operating terminal temperature, and the peak instantaneous power of each individual pulse must not exceed the pulse curve limit.

Furthermore, if the resistor's terminal temperature ($T_K$) is already elevated before the surge occurs, the permissible pulse energy must be derated by the available thermal headroom:

$$E_{\text{derated}}=E_{\text{datasheet}}·\left(\frac{T_{\text{max}}-T_K}{T_{\text{max}}-T_{\text{rated}}}\right)$$

Where$T_{\text{max}}$is the ultimate alloy temperature limit (typically${170}^{\circ }\text{C}$for metal plate shunts),$T_{\text{rated}}$is the temperature up to which full power is guaranteed (typically${100}^{\circ }\text{C}\text{--}{120}^{\circ }\text{C}$), and$T_K$is the actual operating terminal temperature.

Steady-State Power and Thermal Drift: Terminal Temperature Derating and TCR

Steady-state current sensing accuracy is governed by conductive heat dissipation into PCB copper and component TCR, requiring verification against Terminal Part Temperature ($T_K$) derating curves^[5] rather than legacy ambient temperature ($T_A$) metrics.

Ambient Temperature ($T_A$) vs. Terminal Part Temperature ($T_K$) Derating

Traditional power resistor sizing relied on ambient temperature ($T_A$) derating curves established during the through-hole era. These legacy curves typically enforce full power up to${70}^{\circ }\text{C}$ambient, derating linearly to zero power at${125}^{\circ }\text{C}$or${155}^{\circ }\text{C}$.

For modern surface-mount metal strip and metal plate shunts, ambient derating is obsolete. Thermal analysis reveals that more than 90% of the heat generated within a low-ohmic surface-mount shunt is dissipated via direct metallic conduction through its solder joints into the PCB copper planes. Natural convection and radiation account for less than 10% of total heat removal.

Consequently, major manufacturers specify derating according to the Terminal Part Temperature ($T_K$or$T_{\text{terminal}}$). Under the$T_K$framework, the shunt maintains 100% rated power dissipation up to terminal temperatures of${100}^{\circ }\text{C}$to${120}^{\circ }\text{C}$. Above this threshold, power derates linearly to zero at$T_{\text{max}}={170}^{\circ }\text{C}$.

To verify steady-state survival, the operating terminal temperature must be evaluated using the internal thermal resistance ($R_{\text{thi}}$) from the resistive element to the solder terminal:

$$T_K=T_{\text{PCB}}+(P_{\text{diss}}·R_{\text{thi}})$$

Applying an ambient derating model to an SMD metal shunt forces engineers to artificially oversize packages (e.g., using a bulky 3921 package where a 2512 would suffice), which increases PCB footprint area, parasitic loop inductance, and component cost.

Element TCR vs. Component TCR: The Copper Lead Pitfall

Temperature Coefficient of Resistance (TCR) defines how much nominal resistance shifts as temperature rises, expressed in parts per million per degree Celsius ($\text{ppm}{/}^{\circ }\text{C}$). A low TCR is essential for maintaining precision in current measurement.

A frequent failure mode in hardware design is conflating the element TCR with the composite component TCR:

• Resistive Alloy TCR: High-stability alloys such as Manganin (copper-manganese-nickel) or Zeranin exhibit an intrinsic TCR between$\pm 15\text{ppm}{/}^{\circ }\text{C}$and$\pm 50\text{ppm}{/}^{\circ }\text{C}$across standard operational temperature ranges ($-{20}^{\circ }\text{C}$to$+{100}^{\circ }\text{C}$).

• Copper Termination TCR: The copper terminals, used to solder the shunt to the board, possess an exceptionally high positive temperature coefficient of$+3900\text{ppm}{/}^{\circ }\text{C}$.

When an electron-beam welded shunt is manufactured, the resistive alloy is fused between two copper terminal blocks. On high-resistance shunts (e.g.,$100\text{m}\Omega$), the copper terminal resistance ($R_{\text{copper}}\approx 0.05\text{m}\Omega$) is negligible compared to the alloy resistance ($R_{\text{alloy}}=99.95\text{m}\Omega$).

Conversely, for sub-milliohm shunts (e.g.,$0.5\text{m}\Omega$to$1\text{m}\Omega$), the terminal copper contributes a substantial fraction of the total component resistance. If voltage sense lines are connected to external copper terminations rather than isolated across the alloy, the high TCR of the copper corrupts the composite performance:

Component TCR on Sub-Milliohm 2-Terminal Shunt: R_total = R_alloy (TCR = ±20 ppm/°C) + R_copper (TCR = +3900 ppm/°C) Result: Composite TCR jumps to ±100 ppm/°C to ±275 ppm/°C.

The resulting thermal drift over temperature can be modeled as:

$$\Delta R_{\text{thermal}}=R_{\text{nom}}·[{\text{TCR}}_{\text{composite}}·(T_K-{25}^{\circ }\text{C})]$$

If an engineer sizes a$1\text{m}\Omega$shunt for a$100\text{A}$continuous bus ($P_{\text{diss}}=10\text{W}$) and assumes a datasheet element TCR of$\pm 20\text{ppm}{/}^{\circ }\text{C}$, but the 2-terminal assembly exhibits a composite TCR of$+250\text{ppm}{/}^{\circ }\text{C}$, an${80}^{\circ }\text{C}$terminal rise introduces a$+2.0\%$systematic measurement gain error—completely exceeding the 0.5% system tolerance budget before analog amplifier errors are even introduced.

Kelvin (4-Terminal) Connection Architectures and PCB Layout

Kelvin 4-terminal connections isolate high-current paths from voltage sense lines, eliminating measurement gain errors of up to 50% caused by parasitic solder joint resistance and thermal copper drift on sub-$10\text{m}\Omega$shunts.

Parasitic Resistance in Sub-Milliohm Solder Joints

In a standard two-wire sensing configuration, high load current flows directly through the same solder pads and copper traces used to sample the sense voltage.

A standard surface-mount solder joint using lead-free SAC305 alloy introduces an interface contact resistance between$0.1\text{m}\Omega$and$0.5\text{m}\Omega$, depending on solder paste volume, wetting quality, and intermetallic compound thickness. In addition, the SAC305 solder alloy exhibits a high temperature coefficient of resistance of approximately$+3900\text{to}+4000\text{ppm}{/}^{\circ }\text{C}$.

When measuring large resistances (e.g.,$1\Omega$), an extra$0.4\text{m}\Omega$of series solder resistance is negligible ($+0.04\%$error). However, on low-ohmic shunts required in modern multi-kilowatt power electronics:

• Nominal Shunt Value:$R_{\text{nominal}}=1.0\text{m}\Omega$

• Total Parasitic Solder Resistance:$2\times R_{\text{solder}}\approx 0.4\text{m}\Omega$

• Total Measured Resistance:$R_{\text{measured}}=1.4\text{m}\Omega$

This adds an uncalibrated$+40\%$systematic measurement error. As the system heats up under load, the solder's$+4000\text{ppm}{/}^{\circ }\text{C}$TCR causes rapid reading drift.

For any shunt resistor with a resistance value below$10\text{m}\Omega$, and especially below$5\text{m}\Omega$, standard 2-wire sensing cannot deliver reliable accuracy. Implementing a 4-terminal Kelvin connection^[2] is mandatory.

Dedicated 4-Terminal Packages vs. 4-Pad Kelvin PCB Layouts

To isolate parasitic solder and terminal resistance, engineers must implement Kelvin sensing, separating the circuit into two distinct loops:

1. Force / Current Path: Carries the high system load current through the main termination pads.

2. Sense / Voltage Path: Connects directly across the resistive element into the high-impedance inputs of a Current Sense Amplifier (CSA), drawing negligible current ($<1\mu \text{A}$) and therefore dropping zero voltage across sense line solder joints.

Engineers typically select between two practical implementations:

• Dedicated 4-Terminal Components: The physical resistor package provides four distinct pins. Internally, the voltage sense terminals tap directly into the central resistive alloy, physically decoupled from the high-current lugs. This provides high measurement accuracy and eliminates reliance on PCB layout tolerances, but carries a 30% to 100% component cost premium.

• 4-Pad Kelvin Split Footprints for 2-Terminal Packages: When component bill-of-materials (BOM) cost or footprint availability restricts the design to standard 2-terminal SMD packages (such as 2512 or 1206), a 4-pad split layout must be etched into the PCB. The PCB footprint divides each terminal into an outer high-current pad and an inner sense pad, separated by an etched solder-mask slit ($0.15\text{to}0.25\text{mm}$wide).

While split pads on 2-terminal devices significantly improve accuracy, they cannot fully eliminate errors from solder meniscus height variations across manufacturing runs. The solder fillet under a 2-terminal part creates an irregular current path, meaning split 2-terminal layouts typically achieve$0.5\%\text{--}1\%$production accuracy, whereas native 4-terminal components reliably deliver$<0.1\%\text{--}0.5\%$accuracy.

Guidance on routing the sense traces for these layouts is detailed in ROHM’s application note on PCB layout of shunt sensing lines^[3].

Thermal EMF (Seebeck Effect) and DC Offset Suppression

Whenever dissimilar metals meet, a thermocouple is formed. When a temperature gradient ($\Delta T$) exists across the resistor body, the two junctions generate a thermoelectric voltage known as Thermal EMF (Seebeck Effect):

$$V_{\text{EMF}}=S_{\text{metal1-metal2}}·(T_{\text{junction1}}-T_{\text{junction2}})$$

In low-voltage, high-current sensing, where the full-scale differential sense voltage ($V_{\text{sense}}=I·R$) is only$20\text{to}50\text{mV}$, even microvolts of Thermal EMF introduce substantial zero-current DC offset errors:

• Constantan (Cu-Ni) against Copper: Generates an uncompensated Seebeck coefficient of approximately

  $+40\mu \text{V}{/}^{\circ }\text{C}$

  . If asymmetric airflow or adjacent MOSFET heating induces a modest

  ${20}^{\circ }\text{C}$

  temperature difference across the shunt body, the resulting thermal EMF is:

  $$V_{\text{EMF}}=40\mu \text{V}{/}^{\circ }\text{C}·{20}^{\circ }\text{C}=800\mu \text{V}=0.8\text{mV}$$

  On a$20\text{mV}$full-scale current range, this represents a massive$+4\%$DC measurement offset.

• Manganin or Zeranin against Copper: Features a matched thermoelectric coefficient of$<0.6\text{to}1.0\mu \text{V}{/}^{\circ }\text{C}$($<0.6\mu \text{V}/\text{K}$). The identical${20}^{\circ }\text{C}$gradient generates only$12\text{to}20\mu \text{V}$, maintaining negligible error.

To suppress Thermal EMF in board layouts:

1. Symmetrical Copper Geometry: Ensure both terminal pads connect to equal copper mass and identical layer stack transitions, preventing asymmetric heatsinking.

2. Perpendicular Placement: Orient the long axis of the shunt resistor perpendicular to the dominant direction of airflow or heat plumes from adjacent switching MOSFETs.

Parasitic Inductance (ESL) and Noise Management in High di/dt Environments

Parasitic Equivalent Series Inductance (ESL) generates voltage spikes proportional to$L_{\text{ESL}}·\frac{di}{dt}$, which can exceed the real current signal by several hundred percent during fast switching transitions and trigger false overcurrent protection trips.

How To Measure Extreme Pulsed Currents (Pulsed Shunts Part 1)

The$L·\frac{di}{dt}$Inductive Spike Mechanism

An actual current shunt resistor is not an ideal ohmic resistance. It must be modeled as a pure resistance ($R$) in series with an Equivalent Series Inductance ($L_{\text{ESL}}$), accompanied by mutual inductive coupling ($M$) into the PCB sensing loop:

$$V_{\text{measured}}(t)=R·i(t)+(L_{\text{ESL}}+M)\frac{di}{dt}$$

In visual stress tests and circuit modeling, we observe that measured voltage includes both the internal component inductance$L$and loop mutual inductance$M$, which easily reaches$0.1\text{to}1\mu \text{H}$when connected to standard oscilloscope test fixtures without tightly controlled loop geometry.

In modern power electronics utilizing fast silicon Superjunction MOSFETs, Silicon Carbide (SiC) MOSFETs, or Gallium Nitride (GaN) HEMTs, switching speeds routinely reach current slew rates of:

$$\frac{di}{dt}\ge 100\text{A}/\mu \text{s}=100\times {10}^6\text{A/s}$$

Consider a standard longitudinal 2512-package metal strip shunt ($5\text{m}\Omega$) with a parasitic inductance$L_{\text{ESL}}\approx 2\text{nH}$operating in a$10\text{A}$stage:

• True Resistive Signal:

  $$V_R=I·R=10\text{A}·5\text{m}\Omega =50\text{mV}$$

• Parasitic Inductive Voltage Spike:

  $$V_L=L_{\text{ESL}}·\frac{di}{dt}=2\text{nH}·100\times {10}^6\text{A/s}=200\text{mV}$$

• Total Peak Measured Voltage:

  $$V_{\text{measured}}=50\text{mV}+200\text{mV}=250\text{mV}$$

The inductive spike is 400% larger than the legitimate measurement signal. When routed to an analog comparator for fast Over-Current Protection (OCP) or short-circuit desaturation detection, this inductive spike triggers immediate false trips at normal load currents.

Package Geometry Sizing: Standard vs. Reverse-Geometry Wide Terminals

Parasitic inductance is fundamentally dictated by physical geometry: the length of the current path and the loop area enclosing the magnetic flux.

Standard aspect ratio packages (e.g., 2512, 1206) force current to flow down the long axis of the component. This extended current loop results in internal series inductance values typically between$2\text{nH}$and$5\text{nH}$.

To counter this, high-speed switching circuits utilize wide-terminal / reverse-geometry packages (such as 0612, 1225, or 1020). By rotating the terminations by 90 degrees, current flows across the short transverse width rather than the length:

• Shorter Path: Conduction length is reduced by up to 75%, cutting$L_{\text{ESL}}$down to$<0.5\text{to}1.0\text{nH}$.

• Wider Conduction Entry: Current density is distributed over a broader solder interface, which simultaneously lowers thermal resistance ($R_{\text{thi}}$) and enhances steady-state power dissipation ratings by up to $100\%$ compared to standard packages of identical area.

The Low-Resistance Paradox and Sense Loop Filtering

A common counter-intuitive challenge in fast-pulse measurement is the low-resistance paradox. When designers encounter thermal overstress, they instinctively select lower resistance values to reduce$I^{2}R$conduction loss. However, decreasing$R$severely degrades the signal-to-noise ratio during fast switching transients.

The fractional measurement error ($\Delta$) caused by parasitic inductance during a fast pulse with rise time$t_r$is approximated by:

$$\Delta \approx \frac{V_L}{V_R}\approx \frac{1}{t_r}·\frac{L_{\text{ESL}}}{R}$$

To maintain an acceptable measurement error ratio below 10% ($\Delta \le 0.1$), the shunt's internal time constant must satisfy:

$$\frac{L_{\text{ESL}}}{R}\le 0.1·t_r$$

As resistance$R$drops into the sub-milliohm territory, the denominator shrinks, causing the relative error ratio ($\frac{L}{R·t_r}$) to skyrocket. Higher resistance shunts yield larger true resistive voltage drops ($R·i$) that effectively swamp inductive noise ($L\frac{di}{dt}$), provided the resistor's thermal rating is respected.

In visual stress tests, we observed that an underdamped LC discharge captured across a$1\Omega$shunt yielded a clean, recognizable curve with only a minor inductive leading-edge spike. In contrast, testing across a$0.1\Omega$shunt resulted in severe distortion where the$L\frac{di}{dt}$spike completely dwarfed and corrupted the real current waveform into chaotic ringing. Experts point out that engineers must treat every waveform with caution and not mistake a narrow inductive spike for a genuine kiloamp surge.

To suppress ESL inductive distortion without sacrificing power efficiency, two layout and circuit countermeasures are required:

1. Bifilar Sense Loop Routing: Visual inspection of parasitic loops shows that folding the sensing traces into a "bifilar loop" minimizes the enclosed magnetic area$A$. Routing sense traces directly atop one another on adjacent PCB layers (e.g., Layer 1 sense positive, Layer 2 sense negative) creates opposing mutual flux linkages ($+M$and $-M$), canceling mutual inductance down to$0.5\text{to}5\text{nH}$.

2. Pole-Zero Canceling RC Filter: A low-pass differential filter (

   $R_f{C}_f$

   ) placed directly across the amplifier inputs eliminates the inductive zero created by

   $L_{\text{ESL}}$

   . By matching the filter time constant to the shunt's inductive time constant:

   $$\tau =R_f·C_f\approx \frac{L_{\text{ESL}}}{R_{\text{shunt}}}$$

   The low-pass pole cancels the ESL differentiator zero, restoring flat frequency response and preventing false comparator tripping without introducing unnecessary phase lag into the current feedback control loop.

Engineering Verification Workflow: Dual-Checklist Decision Framework

Safe shunt sizing decouples the design verification into two independent checks: the Steady-State Thermal Loop (ensuring long-term stability and allowable drift) and the Startup & Inrush Pulse Loop (preventing adiabatic component destruction).

The Steady-State Thermal Loop Checklist

1. Calculate continuous average dissipation:$P_{\text{avg}}=(I_{\text{rms}}{)}^2·R$.

2. Measure or model the terminal part temperature:$T_K=T_{\text{PCB}}+(P_{\text{avg}}·R_{\text{thi}})$.

3. Verify that$P_{\text{avg}}\le P_{\text{derated}}(T_K)$using the manufacturer’s terminal temperature derating curve.

4. Calculate total thermal drift:$\Delta R=R_{\text{nom}}·{\text{TCR}}_{\text{comp}}·\Delta T$.

5. Check that the total RSS error budget remains within specification.

The Startup & Inrush Pulse Loop Checklist

1. Calculate pulse energy:$E_{\text{pulse}}={\int }_0^{t_p}{i}^2(t)Rdt$.

2. Determine equivalent peak power:$P_{\text{eq}}=E_{\text{pulse}}/t_p$.

3. Check the pulse duration regime: is$t_p<1\text{to}10\text{ms}$(adiabatic heating)?

4. Verify that$E_{\text{pulse}}\le E_{\text{datasheet}}(t_p)$with at least 30% margin.

5. Apply thermal headroom derating if$T_K$is elevated before the surge.

6. Calculate inductive kick:$V_L=L_{\text{ESL}}·(di/dt)$and verify it does not trip OCP.

The PCB Layout & Architecture Check

1. Is

   $R_{\text{shunt}}<5\text{m}\Omega$

   to

   $10\text{m}\Omega$

   ?

• YES: Enforce a 4-terminal Kelvin architecture.

• NO: A standard 2-pad footprint is

  References

1. 12 Things to Know About Resistors in Pulse Load Applications — Vishay Intertechnology, Inc.

2. Optimize High-Current Sensing Accuracy by Improving Pad Layout of Low-Value Shunt Resistors — Analog Devices, Inc.

3. Guide for PCB Layout of Sensing Lines Using Shunt Resistor (Application Note) — ROHM Co., Ltd.

4. Shunt Selection Guideline (White Paper 08/2024) — Isabellenhütte Heusler GmbH & Co. KG

5. Introduction of the Derating Curves Based on the Terminal Part Temperature — KOA Corporation / KOA Speer Electronics, Inc.

6. Optimal Layout Practices for Low-Ohmic Current Sense Resistors in Parallel — Texas Instruments Incorporated

7. JIS C 5201-1: Fixed Resistors for Use in Electronic Equipment - Part 1: Generic Specification — Japanese Standards Association