Structure and Working Principle of Field Effect Transistors

Field Effect Transistors (FETs) represent a fundamental building block in modern electronics, implementing critical functions in virtually all contemporary electronic devices. These semiconductor devices control output circuit current through the electric field effect in the control input circuit, earning their distinctive name. Unlike bipolar junction transistors, FETs operate using only majority carriers (either electrons or holes), which is why they are classified as unipolar transistors (Sedra & Smith, 2020). The two primary categories of FETs are Junction Field Effect Transistors (JFETs) and Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), each with distinct operational characteristics and applications.

Catalog

I Structure and Working Principle

Field-effect transistors are divided into two categories: junction field-effect transistors (JFET) and metal oxide semiconductor field-effect transistors(MOSFET).

Field-effect transistors can be categorized based on several criteria. According to channel material and gate type, they are classified as either N-channel or P-channel transistors. From a conduction perspective, FETs are categorized as either depletion-type or enhancement-type devices. While JFETs are exclusively depletion-type, MOSFETs can be configured as either depletion or enhancement types, offering designers greater flexibility (Razavi, 2021).

1. Junction Field Effect Transistor

(1) Structure

The N-channel JFET exhibits a distinctive structure wherein two PN junctions sandwich an N-type channel (see Figure 1). This configuration is created by fabricating PN junctions on opposite sides of an N-type semiconductor silicon substrate. The two P-regions constitute the gate terminals, while the ends of the N-type silicon form the drain and source terminals respectively (Neamen, 2022).

Figure 1. Structure of the Junction Field Effect Transistor

(2) Working Principle

Take the N-channel as an example to illustrate its working principle.

In N-channel JFETs, when the gate-source voltage (VGS) equals zero and a voltage potential is applied between drain and source, majority carriers (electrons) drift between these terminals, generating a drain current (ID). When VGS becomes negative, the PN junctions enter reverse-bias, creating depletion regions that narrow the conductive channel. This channel constriction increases the resistance to current flow, causing ID to decrease (Boylestad & Nashelsky, 2020).

As VGS continues to decrease (becoming more negative), the depletion regions expand further, progressively narrowing the channel until ID approaches zero. The gate-source voltage at which the channel becomes completely depleted and drain current ceases is termed the pinch-off voltage, denoted as VGS(off). This mechanism provides the fundamental means of controlling current flow in JFETs (Sze & Ng, 2021).

(3) Characteristic Curve of Junction Field-Effect Transistors

There are two characteristic curves of the junction field-effect transistor,

One is the output characteristic curve (ID=f(VDS) | VGS=constant), the second is the transfer characteristic curve (ID=f(VGS)|VDS=constant).

The characteristic curve of the N-channel junction field effect transistor is shown in the figure below.

(A) Drain Output Characteristic Curve       (b) Transfer Characteristic Curve

Figure 2. The Characteristic Curve of the N-channel Junction Field Effect Transistor

JFETs exhibit two characteristic relationships that define their electrical behavior:

1. Output characteristic curve: This plots drain current (ID) against drain-source voltage (VDS) for constant values of gate-source voltage (VGS). It illustrates how drain current changes with drain-source voltage under different gate bias conditions.

2. Transfer characteristic curve: This represents the relationship between drain current (ID) and gate-source voltage (VGS) at a constant drain-source voltage (VDS). This curve demonstrates the transistor's current-controlling capabilities (Streetman & Banerjee, 2020).

2. Metal-oxide Semiconductor FET

Metal-oxide semiconductor field-effect transistors are divided into:

Depletion type → N channel, P channel

Enhancement type → N-channel, P-channel

(1) Structure of N-channel Depletion Type FET

The structure and symbol of the N-channel depletion-mode are shown in the following figure (a). The SiO2 insulating layer under the gate is doped with a large number of positive metal ions. So when VGS=0, these positive ions have induced the inversion layer, forming a channel. Therefore, as long as there is a drain-source voltage, there is a drain current.

When VGS>0, the ID will increase. When VGS <0, the drain current gradually decreases as VGS decreases until ID=0. The VGS when ID=0 is called the pinch-off voltage, represented by the symbol VGS (off) or VP sometimes.

The transfer characteristic curve of the N-channel depletion-mode is shown in figure (b) below.

(a) Structure diagram (b) Transfer characteristic curve

Figure 3. The Structure and Transfer Characteristic Curve of the N-channel Depletion Mode

(2) N-channel Enhancement Type FET

N-channel enhancement type field effect transistor has a structure similar to that of depletion mode. But when VGS = 0V, adding a voltage between the drain and source will not form a current. When a voltage is applied to the gate, if VGS>VGS (th), a channel is formed, connecting the drain and the source. If the drain-source voltage is applied at this time, an ID can be formed.

When VGS=0V, ID=0, and the drain current of the enhancement type will appear only after VGS>VGS (th).

VGS (th)-opening voltage or valve voltage;

Figure 4. N-channel Enhancement Type FET

(3) P-channel Enhancement Mode and Depletion Mode MOSFET

The working principle of the P-channel MOSFET is exactly the same as that of the N-channel MOSFET, except that the conductive carriers and the polarity of the supply voltage are different. This is similar to the NPN and PNP types of bipolar transistors.

3. Volt-ampere Characteristic Curve of FET

There are many types of characteristic curves of field-effect transistors. There are four transfer characteristic curves and output characteristic curves according to different conductive channels and whether they are enhanced or depleted, and their voltage and current directions are also different. If the positive direction is uniformly specified, the characteristic curves will be drawn in different quadrants. In order to facilitate drawing, the positive direction of the P-channel transistor is reversed. The relevant curves are drawn in the figure below.

Figure 5. Volt-ampere Characteristic Curve of Field-Effect Transistors

4. Comparison of various FET characteristics

(a) Transfer Characteristic Curve (b) Output Characteristic Curve

Figure 6. Comparison of various FET characteristics

II Field Effect Transistor Parameters

There are many parameters of field-effect transistors, including DC parameters, AC parameters, and limit parameters, but in general, we only need to pay attention to the following parameters.

(1) Pinch off Voltage (UP)

This refers to the voltage UGS applied to the gate when the drain current /D (ie, channel current) is zero or less than a small current value (for example, 1μA. 10μA) under the specified drain voltage UDS. It is an important parameter of junction or depletion type MOS field-effect transistors.

(2) Turn-on Voltage (UT)

This is the gate voltage UGS when the conductive channel (between the drain and the source) is just turned on when the drain voltage UDS is at a certain value. It is an important parameter of the enhancement field-effect transistor. When the gate voltage UGS is less than the absolute value of the turn-on voltage, the field-effect transistor cannot be turned on.

(3) Saturation Leakage Current (DSS)

It refers to the saturation leakage current of the drain current D caused by a certain drain voltage UDS (greater than the pinch-off voltage) when the gate and source are shorted (UGS=0). It reflects the conduction capability of the original channel at zero gate voltage, which is an important parameter of depletion field-effect transistors.

(4) Low-frequency Transconductance (gm)

When the drain voltage UDS is at a specified value, the ratio of the drain current change to the gate voltage change △UGS that causes this change is called transconductance, that is:

The common unit of gm is mS (millisiemens). gm is a parameter that measures the strength of the gate voltage of the field-effect transistor on the control of the drain current, as well as the amplification effect. It is similar to the AC amplification factor of the transistor β and is related to the working area of the transistor. The greater the drain current /D, the greater the gm.

(5) Drain Source Breakdown Voltage (BUDS)

This refers to the maximum drain voltage that the field-effect transistor can withstand when the gate voltage UGS is constant. It is equivalent to the collector-emitter breakdown voltage V(BR)ceo (ie BUceo) of a common crystal transistor. This is a limit parameter, and the working voltage applied to the field-effect transistor must be less than BUDS.

(6) Maximum Drain-source Current (DSM)

This refers to the maximum current allowed between the drain and the source when the field-effect transistor is working normally. It is equivalent to the operating current of the common crystal transistor. This limit parameter should not be exceeded.

(7) Maximum Power Dissipation (PDSM)

This refers to the maximum drain power dissipation allowed when the performance of the field-effect transistor does not deteriorate, which is equivalent to the Pcm of an ordinary transistor. When in use, the actual power consumption of the field-effect transistor (PD=UDS&times;/D) should be less than this limit parameter, and leave a certain margin.

III Field Effect Transistor Testing Method

1. Pin Identification of JFET

The gate of the field-effect transistor is equivalent to the base of the transistor, and the source and drain correspond to the emitter and collector of the transistor, respectively. Set the multimeter to “R×1k”, and use two test leads to measure the forward and reverse resistance between every two pins. When the positive and reverse resistances of two pins are both several thousand ohms, then these two pins are the drain and the source (interchangeable), and the remaining pin is the gate. For junction field-effect transistors with 4 pins, the other pole is the shielding pole (grounding when in use).

2. Gate Judgement

Connect the black test lead of the multimeter to one electrode of the transistor, and the red test to the other two electrodes respectively. If the resistance values measured twice are very large, it means that they are reverse resistances. So it is an N-channel field-effect transistor, and the black lead is connected to the gate.

Figure 7. Test FET with Multimeter

The manufacturing process determines that the source and drain of the field-effect transistor are symmetrical and can be used interchangeably without affecting the normal operation of the circuit, so there is no need to distinguish them. The resistance between the source and drain is about several thousand ohms.

Note that this method cannot be used to determine the gate of a MOSFET. Because the input resistance of MOSFET is extremely high, and the interelectrode capacitance between the gate and the source is very small, as long as there is a small number of charges during measurement, a high voltage can be formed on the inter-electrode capacitance, which is easy to damage the transistor.

3. Amplification Estimation

Set the multimeter to “R×100”, and connect the red test lead to the source, and the black test lead to the drain, which is equivalent to adding a 1.5V power supply voltage to the field-effect transistor. At this time, the pointer indicates the resistance value between the drain and the source.

Then pinch the gate with your finger to apply the induced voltage of the human body as an input signal to the gate. Due to the amplification effect of the transistor, both UDS and ID will change, which means the resistance between the drain and source also changes, and the test lead swings greatly. If the swing is little when you pinch the gate, it means the transistor's magnification ability is weak; if the lead does not move, it means the transistor has been damaged.

Because the 50Hz AC voltage induced by the human body is rather high, and different field-effect transistors may have different working points when measured with the resistance gear, the hands may swing to the right or the left when the gate is pinched by hand. When the RDS of the transistors decreases, the test lead swings to the right, while it swings to the left if RDS increases.

Regardless of the swing direction of the hands, as long as there is a clear swing, it means that the transistor can amplify.

This method is also suitable for measuring MOS transistors. In order to protect the MOS field-effect transistor, it is necessary to hold the insulating handle and connect the gate with a metal rod to prevent the human body-induced charge from being directly added to the gate and damaging the transistor.

After each measurement of the MOS transistor, there will be a small number of charges on the G-S junction capacitor, and the voltage UGS will be established. Then, if you continue the test, the test lead may not move, and short-circuit the circuit between the G-S pole will solve the problem.

IV Precautions

1. In order to use the field-effect transistor safely, in the circuit design, limit parameters such as the power dissipation, the maximum drain-source voltage, the maximum gate-to-source voltage, and the maximum current must not be exceeded.

2. When using various types of field-effect transistors, they must be inserted into the circuit in strict accordance with the required bias, and observe the polarity of the bias of the field-effect transistor. For example, there is a PN junction between the source and drain of the junction field-effect gate, so the N-channel gate cannot be positively biased, and the P-channel gate cannot be negatively biased.

3. Due to the extremely high input impedance of the MOS field-effect transistor, the lead-out pins must be short-circuited during transportation and storage. Besides, the metal shielding package should be used to prevent the externally induced potential from breaking the gate.

In particular, it's better to store the MOS field-effect transistor in a metal box rather than a plastic box. Also, the moisture resistance of the transistor should be noted.

4. In order to prevent the gate induction breakdown of the field-effect transistor, all test instruments, workbenches, electric irons, and the circuit itself must be well-grounded, which means:

(1) When you solder the pins, first solder the source electrode.

(2) Before connecting to the circuit, all the lead ends of the transistor are kept shorted to each other, and the shorting material is removed after welding.

(3) When you remove the transistor from the component rack, the human body should be grounded appropriately, like using a ground ring.

(4) If you use the advanced gas-heating electric soldering iron, it is more convenient to weld the field-effect transistor but you should ensure safety.

Figure 8. Gas-heating Soldering

(5) it is absolutely not allowed to insert or pull the transistor into the circuit without turning off the power.

5. When installing the field-effect transistor, the installation position should be kept as far as possible from the heating element. And in order to prevent the vibration of the transistor, it is necessary to fasten the transistor shell. Also, when we bend the pin lead, it should be carried out 5 mm higher than the root to prevent damaging the pin and causing air leakage.

6. When you use a VMOS transistor, a proper heat sink must be added. Taking VNF306 as an example, the maximum power can only reach 30W after the transistor is equipped with a 140&times;140&times;4 (mm) radiator.

7. After multiple transistors are connected in parallel, the high-frequency characteristics of the amplifier are deteriorated due to the increase in inter-electrode capacitance and distributed capacitance, and it is easy to cause high-frequency parasitic oscillation through feedback. For this reason, there are generally no more than four parallel compound transistors, and the anti-parasitic oscillation resistance should be connected in series on the base or gate of each transistor.

8. The gate-to-source voltage of the junction field-effect transistor cannot be reversed and can be stored in an open state. When the MOS field effect transistor is not in use, because its input resistance is very high, each electrode must be short-circuited to prevent the transistor from being damaged by the external electric field.

9. During the welding, the outer shell of the electric soldering iron must be equipped with an external ground wire to prevent damage to the transistor due to the charged electric iron. For a small amount of soldering, you can also unplug the soldering iron after heating it or cut off the power and solder it. Especially when welding MOS field-effect transistors, the source-drain-gate should be welded in order, and the circuit should be cut off.

10. When welding with a 25W electric soldering iron, the operation should be quick. If you use a 45 to 75W electric soldering iron, use tweezers to clamp the root of the pin to help heat dissipation. Use a multimeter to test the quality of the junction field-effect transistor(like the resistance between the forward and reverse resistance of each PN junction and the drain-source). However, the MOS field-effect transistor cannot be checked with a multimeter, instead, a tester must be used. And the short-circuit line of each electrode can only be removed after connecting the tester. When removing, we should first remove the short circuit and then remove it to avoid the floating gate.

Figure 9. A MOSFET Tester

When there is a high input impedance, moisture-proof measures must be taken to prevent the input resistance of the field-effect transistor from decreasing due to the temperature. If a four-lead field-effect transistor is used, the substrate lead should be grounded. The transistor with a ceramic package is, so it should be protected from the light.

For power FETs, there must be good heat dissipation conditions. Because the power field-effect transistor is used under high load conditions, it is necessary to design enough radiators to ensure that the temperature of the case does not exceed the rated value, so that the device can work stably for a long time.

In short, to ensure the safe use of the field-effect transistor, there are a variety of matters to be noted, and the safety measures are also varied. The vast number of professional and technical personnel, especially electronics enthusiasts, should take practical measures to use field-effect transistors safely and effectively according to their actual situation.

V Field Effect Transistor VS. Transistor

1. The source S, gate G and drain D of the FET correspond to emitter E, base B, and collector C of the transistor respectively, and their functions are similar.

2. FET is a voltage-controlled current device to control ID by VGS and its amplification factor gm is generally small, so the amplification capacity of FET is poor. The transistor is a current-controlled current device to control IC by iB (or iE).

3. The gate of the field-effect transistor absorbs almost no current, while the transistor base absorbs a certain current when it works. Therefore, the input resistance of the FET is higher than that of the transistor.

4. The field-effect transistor is conductive with the majority carriers. The transistor can conduct electricity with the majority and minority carriers. Because the minority carrier concentration is greatly affected by temperature, radiation, and other factors, the FET has better temperature stability and radiation resistance than the transistor.

Figure 10. Majority and Minority Carrier Flow of PNP Transistor

The field-effect transistor should be used when the environmental conditions (temperature, etc.) vary greatly.

5. When the source metal is connected with the substrate, the source electrode, and the drain electrode can be used interchangeably, and their characteristics do not change much. However, if the collector and emitter of the transistor used interchangeably, its characteristics will vary greatly, and the β value will reduce a lot.

6. The noise coefficient of the field-effect transistor is very small, so the field-effect transistor should be selected in the low noise amplifier circuit where the input stage requires a high SNR (signal to noise ratio).

7. Field-effect transistors and transistors can form various and switching circuits, but the FET is more widely used in large-scale and ultra-large-scale integrated circuit due to its simple manufacturing process, low power consumption, good thermal stability, wide working power supply voltage range, and other advantages.

8. The on-resistance of the transistor is large, while that of the field-effect transistor is small, only a few hundred milliohms. In the current electrical devices, field-effect transistors are generally used as a switch for their high efficiency.

Conclusion

Field Effect Transistors represent a cornerstone technology in modern electronics, enabling the development of increasingly powerful, efficient, and compact electronic systems. Their unique operational principles, diverse structural variations, and advantageous characteristics have made them indispensable components in applications ranging from high-speed digital processing to sensitive analog signal amplification. As semiconductor fabrication technology continues to advance, FETs will undoubtedly remain at the forefront of electronic innovation, with ongoing research focusing on overcoming existing limitations while enhancing desirable properties.

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