UC3842 vs UC3845: UVLO, Duty-Cycle Limits, and Startup Design

Executive Engineering Verdict: The Drop-In Replacement Rule

Never substitute a UC3845 directly into a UC3842 circuit, nor a UC3842 into a UC3845 circuit. Although both integrated circuits share an identical 8-pin DIP or SOIC pinout, identical error amplifier topology, and the same internal 5.0 V reference generator, their silicon operating architectures are incompatible.

Direct substitution fails across three hardware parameters:

1. Under-Voltage Lockout (UVLO) Thresholds: The UC3842 turns on at a typical threshold of 16.0 V and shuts down when bias voltage drops below 10.0 V, providing a 6.0 V operating hysteresis window. The UC3845 turns on at 8.4 V to 8.5 V and cuts off at 7.6 V to 7.9 V, providing a narrow hysteresis window of roughly 0.8 V.

2. Maximum Output Duty Cycle Clamp: The UC3842 allows the gate output to switch across duty cycles approaching 100% (practically limited to ~95%–97% by oscillator discharge dead-time). The UC3845 incorporates an internal toggle flip-flop that blanks alternate pulses, enforcing a hard hardware limit of$\le 50\%$^[2] (measured bench maximum ~47%–48%).

3. Switching Frequency Division: The UC3842 switches at the same frequency as its internal timing oscillator ($f_{sw}=f_{osc}$). The UC3845's toggle flip-flop divides the clock by two, causing the gate drive output to switch at half the oscillator frequency ($f_{sw}=\frac{1}{2}{f}_{osc}$).

Placing a UC3845 into an offline flyback power supply engineered around a UC3842 typically triggers one of two failures: perpetual startup hiccup mode (caused by auxiliary winding voltage starvation under duty-cycle clamping) or instantaneous primary MOSFET failure (caused by transformer core saturation when the switching frequency drops by half).

The Architectural Matrix: Deconstructing the UC384x Family

The classic 384x current-mode PWM controller family (originally introduced by Unitrode and standardized by Texas Instruments, STMicroelectronics, and ON Semiconductor) uses a$2\times 2$architectural matrix. The four family members are partitioned by two parameters: UVLO threshold levels and maximum duty cycle capabilities.

For circuit schematics and peripheral pin assignments, refer to the UC3842 PWM Controller Application Circuit & Datasheet^[5] and the UC3845 Circuit, Pinout, and Technical Datasheet^[6].

Topology Suitability Boundaries

• UC3842: Optimized for single-ended offline AC-DC converters where the primary rectified bulk rail ranges from$85{\text{V}}_{AC}$to$265{\text{V}}_{AC}$. At low AC line conditions, continuous conduction mode (CCM) and discontinuous conduction mode (DCM) flyback converters require duty cycles exceeding 50% to maintain secondary voltage regulation without driving peak currents beyond silicon limits.

• UC3845: Optimized for forward converters, push-pull topologies, and DC-DC converters operating from dedicated$12\text{V}$or$24\text{V}$industrial bus rails. In these topologies, exceeding 50% duty cycle risks transformer core saturation due to incomplete flux reset.

Under-Voltage Lockout (UVLO): 16V Offline vs 8.4V DC-DC Operating Windows

The difference in UVLO turn-on and turn-off thresholds between the UC3842 and UC3845 reflects two distinct power-conversion operating environments: offline capacitor charging from rectified line voltage versus startup from low-voltage DC rails.

The Energy Reservoir Physics in Offline AC-DC Power Supplies

Offline power supplies typically power the controller IC during cold startup using a high-value bleeder resistor ($R_{start}$) connected to the rectified mains bulk capacitor ($300\text{V}-400{\text{V}}_{DC}$). Because the bleeder resistor drops hundreds of volts, its current throughput is constrained to 1 mA to 2 mA to limit steady-state power dissipation.

When the controller turns on, its current consumption surges from a quiescent pre-startup level of under 1.0 mA^[1] to an active operating draw of 11 mA to 17 mA, plus the dynamic charge required to drive the external power MOSFET gate ($I_{gate}=Q_g\times f_{sw}$). During this initial burst, the bleeder resistor cannot deliver the operating current. The controller relies entirely on energy stored inside the local$V_{CC}$bypass capacitor ($C_{VCC}$) until the transformer's auxiliary bootstrap winding develops sufficient rectified voltage to sustain the rail.

The usable electrical energy stored in the reservoir capacitor before the controller reaches UVLO shutdown is:

$$\Delta E=\frac{1}{2}{C}_{VCC}(V_{UVLO(on)}^2-V_{UVLO(off)}^2)$$

Evaluating a standard$47\mu \text{F}$aluminum electrolytic reservoir capacitor on both ICs:

• UC3842 Operating Window:

  $$\Delta E_{3842}=\frac{1}{2}\times (47\times {10}^{-6}\text{F})\times ({16.0}^2-{10.0}^2)=0.5\times (47\times {10}^{-6})\times (256-100)\approx 3.666\text{mJ}$$

• UC3845 Operating Window:

  $$\Delta E_{3845}=\frac{1}{2}\times (47\times {10}^{-6}\text{F})\times ({8.4}^2-{7.6}^2)=0.5\times (47\times {10}^{-6})\times (70.56-57.76)\approx 0.301\text{mJ}$$

The UC3842 provides more than 12 times the startup energy buffer ($3.666\text{mJ}$vs.$0.301\text{mJ}$) of the UC3845 for the same capacitor value. In an offline circuit, the 0.8 V window of the UC3845 discharges in a few switching cycles, triggering UVLO cutoff long before the transformer can transfer energy to the secondary outputs and charge the auxiliary bias capacitor.

Gate Drive Integrity at Turn-On

Standard high-voltage power MOSFETs used in offline converters (rated$600\text{V}-800\text{V}$) require gate-to-source voltages ($V_{GS}$) between 10 V and 15 V to achieve full channel enhancement and minimize static on-state resistance ($R_{DS(on)}$).

When the UC3842 turns on at 16.0 V, its totem-pole output driver delivers an initial gate drive pulse of approximately 14.5 V to 15.0 V (accounting for internal bipolar saturation drops), ensuring low conduction losses during peak inrush currents.

Conversely, the UC3845 turns on at 8.4 V to 8.5 V, delivering initial gate pulses of only 7.0 V to 7.5 V. Driving a standard high-voltage MOSFET at 7 V forces the channel into its linear (ohmic) region under heavy primary current loading, creating high conduction losses and risk of thermal failure.

Maximum Duty Cycle and the Internal Toggle Flip-Flop: 100% vs 50%

The second structural difference lies within the digital steering logic between the PWM latch and the output totem-pole driver stage.

The Toggle Flip-Flop Mechanism

In the UC3842, the internal oscillator sets the PWM latch on its trailing edge, and the output (Pin 6) switches high. The output remains high until terminated by either the primary current-sense comparator (Pin 3 reaching the error amplifier threshold) or the oscillator's discharge blanking pulse. Because the driver triggers on every clock cycle, the duty cycle can approach 100%. The maximum attainable duty cycle is governed entirely by the timing capacitor ($C_T$) discharge duration:

$$D_{max}=1-(t_{deadtime}\times f_{osc})$$

For typical timing values ($R_T>5\text{k}\Omega$), dead-time is kept small, allowing practical duty cycles of 95% to 97%.

In the UC3844 and UC3845, an internal toggle (T-type) flip-flop is placed between the oscillator and the output steering logic. The flip-flop changes state on each clock cycle, blanking the gate driver on alternate cycles. Even if the feedback loop commands full output (COMP at Pin 1 pulled high), the output driver cannot conduct for more than half the total switching period. Bench measurements with Pin 2 grounded and Pin 1 pulled to the internal 5 V reference consistently confirm a hard ceiling of 47.5% to 48.5%.

Transformer Flux Balancing in Forward Topologies

This hardware clamping serves a protective role in forward converter topologies. Unlike flyback transformers (which function as coupled inductors storing energy during the switch-on time and transferring it during switch-off), forward transformers transfer energy directly to the output choke while the primary switch conducts.

During switch-off, the transformer's magnetizing inductance must fully demagnetize to prevent core saturation. Enforcing a 50% duty-cycle ceiling guarantees that at least half of every switching period is dedicated to core reset, preventing flux staircase accumulation and transformer failure.

The Frequency Halving Dilemma and Magnetic Core Saturation ($f_{osc}$vs$f_{sw}$)

The internal toggle flip-flop in the UC3845 alters the relationship between the timing network ($R_T/C_T$) at Pin 4 and the output switching frequency at Pin 6.

Oscillator vs. Switching Frequency Relationship

The timing network charges$C_T$via the internal 5.0 V reference through$R_T$and discharges it through an internal constant-current sink. The internal oscillator frequency for the 384x family is calculated according to standard timing formulas^[3] as:

$$f_{osc}\approx \frac{1.72}{R_T\times C_T}$$

• For the UC3842: Gate drive output frequency equals the oscillator frequency:

  $$f_{sw}=f_{osc}$$

• For the UC3845: The toggle flip-flop divides the clock pulses by two:

  $$f_{sw}=\frac{f_{osc}}{2}=\frac{0.86}{R_T\times C_T}$$

When a circuit with$R_T=10\text{k}\Omega$and$C_T=3.3\text{nF}$runs on a UC3842, the oscillator and the gate driver both switch at approximately$48\text{kHz}$to$50\text{kHz}$. Probing the same components with a UC3845 reveals an intact$50\text{kHz}$sawtooth ramp at Pin 4, but a gate drive square wave at Pin 6 operating at $25\text{kHz}$.

The Magnetic Core Saturation Hazard

Swapping a UC3842 with a UC3845 without modifying the timing resistor and capacitor introduces a major core saturation hazard.

Magnetic flux density swing ($\Delta B$) in a power transformer core is governed by Faraday's Law of Induction:

$$\Delta B=\frac{V_{in}\times D}{N_p\times A_e\times f_{sw}}$$

Where:

• $V_{in}$= Rectified DC bulk voltage across the primary winding

• $D$= Operating duty cycle

• $N_p$= Number of primary winding turns

• $A_e$= Core effective cross-sectional area (${\text{m}}^2$)

• $f_{sw}$= Operating switching frequency ($\text{Hz}$)

If a technician substitutes a UC3845 into a UC3842 circuit, the switching frequency ($f_{sw}$) is cut in half while$V_{in}$,$N_p$, and$A_e$remain unchanged. Halving$f_{sw}$doubles the magnetic flux swing ($\Delta B$) required for energy transfer.

Standard Manganese-Zinc (MnZn) power ferrite cores saturate at magnetic flux densities between $0.35\text{T}$and$0.40\text{T}$(3500 to 4000 Gauss) at${100}^{\circ }\text{C}$. Most offline power supply transformers are engineered to operate at peak flux densities ($B_{max}$) between$0.18\text{T}$and$0.25\text{T}$under full-load and low-line conditions, maintaining a safe margin below saturation.

Doubling the operating flux swing drives the ferrite core deep into magnetic saturation. When saturation occurs:

1. Primary magnetizing inductance collapses toward the air-core value ($L_p\to L_{air}$).

2. Primary current rises rapidly, exceeding the di/dt handling capacity of the controller.

3. The internal current-sense comparator propagation delay (~150 ns) becomes too slow to terminate the pulse before current exceeds the MOSFET's pulsed current rating ($I_{DM}$).

4. The primary MOSFET suffers instantaneous drain-to-source breakdown, often destroying the current-sense resistor and the PWM controller in the process.

Why Replacing UC3842 with UC3845 Causes Startup Failure (The "Hiccup Trap")

When an improper swap does not cause destructive saturation, the supply typically enters an endless cyclic restart sequence known as hiccup mode, accompanied by an audible ticking sound from the transformer.

{779} Comparison between UC3842, UC3843, UC3844, UC3845 ICs

The Step-by-Step Failure Sequence

1. Low-Threshold Premature Triggering: Mains voltage charges$C_{VCC}$through the high-value startup resistor. The UC3845 reaches its turn-on threshold at$8.5\text{V}$instead of waiting for the design-intended$16.0\text{V}$. The controller wakes up with only a fraction of the capacitive energy required for startup.

2. Duty-Cycle Starvation During Inrush: When the converter starts, the secondary output filter capacitors are completely uncharged, acting as a momentary short circuit. In a flyback converter, transferring enough energy to build up secondary voltage quickly requires long duty cycles ($>50\%$). The UC3845's internal flip-flop clamps pulse widths to roughly 48%, starving secondary power delivery.

3. Auxiliary Rail Handover Failure: Because power transfer is restricted by duty-cycle clamping, the output voltages rise slowly. The transformer's auxiliary winding cannot produce sufficient flyback voltage to reverse-bias the bootstrap diode and support the$V_{CC}$rail before the stored charge in$C_{VCC}$is depleted.

4. Hysteresis Depletion and Cutoff: The controller consumes 11 mA to 17 mA while discharging$C_{VCC}$. Because the hysteresis window is only 0.8 V ($8.5\text{V}\to 7.6\text{V}$),$V_{CC}$drops below$7.6\text{V}$within milliseconds. The UC3845 turns off, and switching stops.

5. Continuous Ticking Cycle: With switching halted, the IC reverts to its sub-milliampere standby state ($I_{start}\le 1.0\text{mA}$). The startup resistor slowly recharges$C_{VCC}$from$7.6\text{V}$back to$8.5\text{V}$. Once$8.5\text{V}$is reached, the IC triggers again, discharges immediately, and shuts down, cycling indefinitely, a common pattern observed in bench repair troubleshooting^[7].

Failure Modes by Swap Direction

Startup Circuit Engineering: Sizing$R_{start}$,$C_{VCC}$, and the Auxiliary Handshake

Designing a reliable startup circuit requires balancing pre-startup bleeder currents against reservoir capacitor holdup time and auxiliary winding reflections.

Sizing the Startup Resistor ($R_{start}$)

The startup resistor must deliver enough current to cover the controller's pre-startup current draw ($I_{start}$) while maintaining margin under minimum DC input conditions:

$$R_{start(max)}\le \frac{V_{DC\_bus(min)}-V_{UVLO(on)}}{I_{start(max)}}$$

Where:

• $V_{DC\_bus(min)}$= Minimum rectified DC bus voltage (typically$\approx 100{\text{V}}_{DC}$for an$85{\text{V}}_{AC}$universal input line).

• $V_{UVLO(on)}$= Controller maximum turn-on threshold ($17.5\text{V}$for UC3842;$9.0\text{V}$for UC3845).

• $I_{start(max)}$= Maximum pre-startup quiescent current ($1.0\text{mA}$^[4] across the UC384x series).

For reliable operation across component tolerances and ambient temperatures, engineers typically design for a bleeder current of$1.5\text{mA}$to$2.0\text{mA}$.

To handle electrical stress, verify power dissipation and voltage withstand ratings under maximum line conditions ($V_{DC\_bus(max)}\approx 375{\text{V}}_{DC}$for$265{\text{V}}_{AC}$mains):

$$P_{R\_start}=\frac{{(V_{DC\_bus(max)}-V_{CC})}^2}{R_{start}}$$

Standard SMD packaging (such as 0805 or 1206) cannot withstand$400\text{V}$continuous DC drops without dielectric breakdown. Offline startup strings should split$R_{start}$across two or three resistors in series (for example, two$68\text{k}\Omega$metal-film resistors) to distribute voltage stress and heat dissipation.

Sizing the Bias Reservoir Capacitor ($C_{VCC}$)

The reservoir capacitor ($C_{VCC}$) must provide power to the IC and drive the MOSFET gate during the startup interval ($t_{startup}$), without dropping below the turn-off threshold:

$$C_{VCC}\ge \frac{I_{operating}\times t_{startup}}{\Delta V_{UVLO(min)}}$$

Where:

• $I_{operating}=I_{CC}+(Q_g\times f_{sw})$(typically$15\text{mA}$to$25\text{mA}$total).

• $t_{startup}$= Time required for secondary outputs and auxiliary winding to reach steady-state conduction (typically$5\text{ms}$to$15\text{ms}$).

• $\Delta V_{UVLO(min)}$= Minimum hysteresis spread ($14.5\text{V}-11.5\text{V}=3.0\text{V}$worst-case for UC3842;$7.8\text{V}-8.2\text{V}$worst-case tolerances for UC3845 require careful margin review).

Because aluminum electrolytic capacitors carry loose initial tolerances ($\pm 20\%$) and lose capacitance as their electrolyte dries at elevated temperatures, designers typically include an additional$2\times$safety factor when calculating$C_{VCC}$for long service life.

Slope Compensation and Peak Current-Mode Control Stability

Both the UC3842 and UC3845 use peak current-mode control, comparing a ramp signal proportional to primary inductor current against an error voltage. However, their differences in duty-cycle capability directly affect loop stability.

The Subharmonic Oscillation Criterion

In any peak current-mode switching regulator operating in continuous conduction mode (CCM), the current control loop becomes inherently unstable whenever the duty cycle exceeds 50% ($D>0.5$).

When an external disturbance alters the inductor current by an increment$\Delta I_0$at the start of a switching period, that disturbance decays by the end of the cycle only if the down-slope of the inductor discharge current ($m_2$) is less than the up-slope of the charging current ($m_1$):

$$\alpha =-\frac{m_2}{m_1}=-\frac{D}{1-D}$$

If$D>0.5$, then$|\alpha |>1$. The perturbation amplifies on every successive clock cycle, causing the PWM controller to alternate between wide and narrow output pulses. This open-loop phenomenon—known as subharmonic oscillation—produces audible transformer buzzing, irregular output ripple, and elevated switch stress.

Architectural Impact on Controller Selection

• The UC3842 (Duty cycles up to 97%): When operating in CCM flyback or boost modes at low line voltages where duty cycle exceeds 50%, the UC3842 requires artificial slope compensation. This is implemented by taking an external emitter-follower transistor or resistor divider from the timing capacitor ramp (Pin 4) and summing a fractional voltage ramp into the current sense input (Pin 3). For optimal noise immunity, route Pin 3 using a dedicated Kelvin sense trace directly across the current-sense shunt resistor with a local low-pass RC filter placed adjacent to the IC pin, suppressing voltage spikes induced by PCB parasitic trace inductance. This added ramp increases the effective charging slope, ensuring stable operation at duty cycles up to 80%–90%.

• The UC3845 (Duty cycle clamped to$\le 50\%$): Because its internal toggle flip-flop prevents the duty cycle from exceeding 50%, the operating condition$|\alpha |>1$cannot occur. The UC3845 is naturally immune to subharmonic oscillation, removing the need for external slope compensation circuits in standard forward and push-pull applications.

Bench Troubleshooting: Proving IC Failure Before Replacement

When troubleshooting an inoperative or clicking power supply on the test bench, technicians often replace the PWM controller first. In practice, passive component degradation in the high-voltage startup and bias network causes the vast majority of offline SMPS startup failures.

Follow this 5-step diagnostic procedure before removing the controller from the PCB:

Step 1: Measure the Rectified High-Voltage DC Bus

With the unit powered via an isolation transformer and series current-limiting bench bulb, measure the voltage across the main primary bulk capacitor ($C_{bulk}$). A healthy offline bridge rectifier should measure approximately$1.41\times V_{AC(in)}$:

• $120{\text{V}}_{AC}$mains:$\approx 160\text{V}-170{\text{V}}_{DC}$

• $230{\text{V}}_{AC}$mains:$\approx 310\text{V}-325{\text{V}}_{DC}$

If this voltage is zero or measures below nominal, inspect the mains fuse, inrush NTC thermistor, and input rectifier diodes before working on the PWM control circuitry.

Step 2: Probe Controller Bias Voltage at Pin 7 ($V_{CC}$)

Connect an oscilloscope or multimeter across Pin 7 ($V_{CC}$) and Pin 5 (GND) to identify the controller's operating state:

• Case A: Voltage is clamped at 0 V to 2 V. The startup resistor string is open, the$V_{CC}$bypass capacitor has suffered dielectric breakdown, or the controller's internal zener protection clamp is shorted.

• Case B: Voltage oscillates in a steady sawtooth pattern between 10.0 V and 16.0 V (for UC3842). The PWM controller is functional and its internal UVLO logic is cycling correctly. The failure typically stems from an overloaded secondary output, a shorted secondary rectifier diode, an open auxiliary bootstrap diode ($D_{aux}$), or a degraded$C_{VCC}$capacitor.

• Case C: Voltage sits stable around 11 V to 14 V, but no switching pulses appear at Pin 6. The IC may be held in shutdown by a low-impedance path pulling Pin 1 (COMP) to ground or Pin 3 (ISENSE) above its 1.0 V threshold, or its internal reference generator has failed.

Step 3: Test High-Value Startup Bleeder Resistors ($R_{start}$)

High-value carbon and metal-film resistors ($100\text{k}\Omega$to$470\text{k}\Omega$) running directly off high-voltage DC lines operate under constant thermal and electrical stress. Over extended service lives, these resistors frequently drift upward in value or fail open. Measure each resistor in the startup chain; a resistor that has drifted 20% to 50% above its nominal value can starve the controller of pre-startup current, preventing Pin 7 from ever reaching its turn-on threshold.

Step 4: Measure ESR and Capacitance of the$V_{CC}$Bypass Capacitor

Electrolytic capacitors placed near primary heat sinks are prone to electrolyte evaporation over time. An ESR increase from$1\Omega$to$10\Omega$in a$22\mu \text{F}-47\mu \text{F}$capacitor limits pulse current delivery during startup, triggering UVLO shutdown even when a multimeter shows the correct nominal DC voltage. Use an in-circuit ESR meter or replace the capacitor with a low-ESR,${105}^{\circ }\text{C}$-rated unit to rule out bias instability.

Step 5: Test the IC with an External Bench Power Supply

To definitively test the controller without dealing with hazardous high-voltage DC rails:

1. Disconnect AC mains power and discharge all high-voltage capacitors.

2. Connect a current-limited DC bench power supply directly across Pin 7 ($V_{CC}$) and Pin 5 (GND). Set the current limit to$30\text{mA}$.

3. For a UC3842, ramp the power supply voltage up to$16.5\text{V}$. For a UC3845, ramp it up to$9.0\text{V}$.

4. Measure Pin 8 ($V_{REF}$). The internal bandgap reference must read $5.00\text{V}\pm 1\%$($4.95\text{V}-5.05\text{V}$). If Pin 8 reads below$4.8\text{V}$or matches$V_{CC}$, the IC's internal reference circuit is damaged.

5. Connect an oscilloscope probe to Pin 6 (OUTPUT). You should observe regular rectangular gate drive pulses matching the frequency set by the Pin 4 timing network.

6. Lower the supply voltage. Verify that gate switching halts cleanly when$V_{CC}$drops past$10.0\text{V}$for the UC3842, or$7.6\text{V}$for the UC3845.

Frequently Asked Questions (FAQ)

Can I replace a UC3842 with a UC3843 in an emergency?

Not directly in an offline AC-DC converter. While both the UC3842 and UC3843 allow duty cycles up to ~97%, the UC3843 uses low UVLO thresholds ($8.4\text{V}$on /$7.6\text{V}$off). In an offline mains circuit designed for 16 V turn-on, the UC3843 will wake up prematurely. Because the stored energy in the reservoir capacitor is too low at 8.4 V, the auxiliary bootstrap winding will fail to take over before$V_{CC}$collapses below 7.6 V, leaving the supply trapped in hiccup mode.

Can I replace a UC3842 with a UC3844?

No. The UC3844 shares the UC3842's 16.0 V turn-on and 10.0 V turn-off UVLO thresholds, but it incorporates the 50% duty-cycle toggle flip-flop. If installed in a single-switch flyback power supply that requires duty cycles over 50% during low mains voltage, the UC3844 will clip the pulse widths, causing output voltage collapse under load. Furthermore, its gate drive will switch at half the original frequency ($f_{sw}=\frac{1}{2}{f}_{osc}$), which risks driving the transformer core into saturation.

What is the pinout difference between the UC3842 and the UC3845?

There is no pinout difference. Both chips use an identical 8-pin package layout: Pin 1 (COMP), Pin 2 (VFB), Pin 3 (ISENSE), Pin 4 (RT/CT), Pin 5 (GND), Pin 6 (OUTPUT), Pin 7 (VCC), and Pin 8 (VREF). The differences are entirely internal—residing in the UVLO comparator reference dividers and the presence of the toggle flip-flop between the PWM latch and the output NOR gate.

Why do some datasheets list the UC3845 UVLO turn-on at 8.4 V and others at 8.5 V?

This minor difference reflects manufacturer-specific silicon revisions and test condition standards. Texas Instruments specifies the UC3845 turn-on threshold at$8.4\text{V}$typical (with an operating band of$7.8\text{V}$minimum to$9.0\text{V}$maximum). ON Semiconductor and STMicroelectronics commonly specify this threshold at$8.5\text{V}$typical. In bench practice, these variations fall within normal manufacturing tolerances and do not affect circuit behavior.

Sources and references used for this guide

1. UCx84x Current-Mode PWM Controllers datasheet (Rev. H)
   Source type: official company documentation
   Used for: Primary manufacturer electrical specifications, UVLO turn-on/turn-off thresholds, internal reference voltage tolerances, and pinout definitions.
   Caution: Official manufacturer datasheet. Note slight typographical parameter differences between commercial (UC384x) and industrial (UC284x) temperature grades.

2. APPLICATION NOTE UC3842/3/4/5 PROVIDES LOW-COST CURRENT-MODE CONTROL (SLUA143)
   Source type: official company documentation
   Used for: Authoritative engineering theory on internal toggle flip-flop operation, 50% maximum duty cycle clamping, and oscillator-to-output frequency halving.
   Caution: Canonical Unitrode/TI engineering application note focused on architectural design theory.

3. UC3842 Provides Low-Cost Current Mode Control (AN246)
   Source type: official company documentation
   Used for: Peak current-mode control loop dynamics, slope compensation circuit requirements for duty cycles exceeding 50%, and oscillator timing formulas.
   Caution: STMicroelectronics vendor application note; represents ST-specific silicon implementation details.

4. UC3842/UC3843/UC3844/UC3845 SMPS Controller Datasheet
   Source type: official company documentation
   Used for: Verification of multi-vendor parametric tolerances (Fairchild/ON Semiconductor), startup current limits, and propagation delay specifications.
   Caution: Authorized distributor hosted datasheet for legacy Fairchild/ON Semiconductor product line.

5. UC3842 PWM Controller Datasheet & Application Circuit
   Source type: reputable professional source
   Used for: Required internal contextual reference covering UC3842 pin configuration, basic application schematics, and peripheral decoupling.
   Caution: Component distributor technical reference article; verify silicon parameters against Tier-1 manufacturer datasheets.

6. UC3845 PWM Controller Circuit, Pinout, and Datasheet
   Source type: reputable professional source
   Used for: Required internal contextual reference covering UC3845 pinout mapping, package dimensions, and typical low-voltage DC-DC circuits.
   Caution: Component distributor technical reference article; verify silicon parameters against Tier-1 manufacturer datasheets.

7. Troubleshooting UC3845 and UC3842 SMPS Startup and Bias Issues
   Source type: community discussion
   Used for: Bench-level troubleshooting insights into auxiliary bootstrap winding collapse, high startup resistor drift, and electrolytic capacitor drying.
   Caution: Community forum thread; used exclusively for understanding practical field failure symptoms and technician diagnostic pitfalls.